Versuch add abgeschlossen. Funktioniert auch praktisch!

2024-11-20 09:44:18 +01:00
parent 641e3a6945
commit 00fd3908d8
72 changed files with 3483 additions and 7 deletions
@@ -72,7 +72,7 @@ begin
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
            when work.task.TASK_RUNNING =>
-                if ( index = work.task.STREAM_LEN - 1 ) then
+                if ( index = work.task.STREAM_LEN  ) then
                    next_task_state <= work.task.TASK_DONE;
                end if;
            when work.task.TASK_DONE =>
@@ -96,10 +96,10 @@ begin
 				if (done_flag = '1') then
 					next_calc_state <= CALC_STORE_RESULT;
 				end if;
-			when CALC STORE RESULT =>
+			when CALC_STORE_RESULT =>
 				next_calc_state <= CALC_IDLE;
 		end case;
-	end process calc state transitions;
+	end process calc_state_transitions;
 	--Zustandsspeicher und Ausgangsschaltnetz zu der Steuerung der Tasks 
@@ -111,7 +111,7 @@ begin
 		elsif (rising_edge( clk)) then
 			current_task_state <= next_task_state; 
 			case next_task_state is
-				when work.task. TASK IDLE => null;
+				when work.task. TASK_IDLE => null;
 				when work.task. TASK_RUNNING => null; 
 				when work.task. TASK_DONE => null;
 			end case;
@@ -127,14 +127,17 @@ begin
 			ergebnis <= (others => '0'); 
 			ergebnis_valid <= '0';
 			signal_write <= '0';
-			signal_writedata <= (others => '0'); 
+			--signal_writedata <= (others => '0'); 
 			signal_a_read <= '0';
 			signal_b_read <= '0';
 		elsif (rising_edge( clk)) then
 			current_calc_state <= next_calc_state; 
 			ergebnis_valid <= '0';
 			case next_calc_state is 
 				when CALC_IDLE =>
 					start_flag <= '0';
-					signal_read <= '0';	--Daten wurden noch nicht verwendet.
+					signal_a_read <= '0';	--Daten wurden noch nicht verwendet.
 					signal_b_read <= '0';
 					signal_write <= '0';
 				when CALC_ADD => 				--hier Berechnung mit IP Core?
 					start_flag <= '1';
@@ -143,7 +146,9 @@ begin
 					index <= index + 1;
 					signal_write <= '1';
 					--signal_writedata <= std_logic_vector( ergebnis ); --Ergebnis schreiben, ergebnis direkt aus IP Core anschliessen
-					signal_read <= '1'	--mitteilen, dass die Daten gelesen wurden und jetzt neue Daten angelegt werden sollen
+					--mitteilen, dass die Daten gelesen wurden und jetzt neue Daten angelegt werden sollen
 					signal_a_read <= '1';	
 					signal_b_read <= '1';
 			end case;
 		end if;
 	end process sync;
@@ -0,0 +1,65 @@
 # vsim -voptargs="+acc" -c work.test_task_add_sine_cosine -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gCHECK_RESULTS=false 
 # Start time: 09:41:58 on Nov 20,2024
 # ** Note: (vsim-3813) Design is being optimized due to module recompilation...
 # ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
 # ** Note: (vopt-143) Recognized 2 FSMs in architecture body "add(rtl)".
 # ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.
 # //  Questa Sim-64
 # //  Version 2023.2 linux_x86_64 Apr 11 2023
 # //
 # //  Copyright 1991-2023 Mentor Graphics Corporation
 # //  All Rights Reserved.
 # //
 # //  QuestaSim and its associated documentation contain trade
 # //  secrets and commercial or financial information that are the property of
 # //  Mentor Graphics Corporation and are privileged, confidential,
 # //  and exempt from disclosure under the Freedom of Information Act,
 # //  5 U.S.C. Section 552. Furthermore, this information
 # //  is prohibited from disclosure under the Trade Secrets Act,
 # //  18 U.S.C. Section 1905.
 # //
 # Loading std.standard
 # Loading std.textio(body)
 # Loading ieee.std_logic_1164(body)
 # Loading ieee.numeric_std(body)
 # Loading ieee.fixed_float_types
 # Loading ieee.math_real(body)
 # Loading ieee.fixed_generic_pkg(body)
 # Loading ieee.float_generic_pkg(body)
 # Loading ieee.fixed_pkg
 # Loading ieee.float_pkg
 # Loading work.reg32(body)
 # Loading work.avalon_slave
 # Loading work.test_utility(body)
 # Loading work.test_avalon_slave(body)
 # Loading work.task(body)
 # Loading work.sine_data
 # Loading work.test_hardware_task(body)
 # Loading work.test_data_channel_pkg(body)
 # Loading std.env(body)
 # Loading work.cosine_data
 # Loading work.sine_cosine_data
 # Loading work.test_task_add_sine_cosine(test)#1
 # Loading work.task_add(struct)#1
 # Loading work.hardware_task_control(rtl)#1
 # Loading work.avalon_slave_transitions(rtl)#1
 # Loading work.add(rtl)#1
 # Loading work.float_add(mixed)#1
 # Loading work.data_channel(struct)#1
 # Loading work.data_channel_control(rtl)#1
 # Loading work.avalon_slave_transitions(rtl)#2
 # Loading work.data_sink_mux(rtl)#1
 # Loading work.fifo(rtl)#1
 # Loading work.data_source_mux(rtl)#1
 # set StdArithNoWarnings 1
 # 1
 #  set NumericStdNoWarnings 1
 # 1
 #  run -all
 # --------------------------------------------------------------------------------
 # Starting test_task_add_sine_cosine
 #     test_configure ... [ OK ]
 #     test_execute ... [ OK ]
 #     write_content ... [ OK ]
 # End time: 09:41:59 on Nov 20,2024, Elapsed time: 0:00:01
 # Errors: 0, Warnings: 1
@@ -0,0 +1,156 @@
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@@ -0,0 +1,4 @@
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 cModel Technology