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This branch is 2 commits behind KutningJo/signal_processing_vorlage:master
Brandl baa5aa4c74 FPGA programmiert
2024-12-18 10:03:57 +01:00
Ergebnisse
FPGA programmiert
2024-12-18 10:03:57 +01:00
hardware
Versuch 3 Hardware funktioniert Juhu!
2024-12-18 09:18:47 +01:00
software
FPGA programmiert
2024-12-18 10:03:57 +01:00
tests
Versuch 3 Hardware funktioniert Juhu!
2024-12-18 09:18:47 +01:00
.gitignore
Initial commit
2023-10-31 07:47:27 +01:00
data_channel_hw.tcl
Initial commit
2023-10-31 07:47:27 +01:00
hardware_task_hw.tcl
Initial commit
2023-10-31 07:47:27 +01:00
hardware_timestamp_hw.tcl
Initial commit
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hdl_sources.qsf
Initial commit
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init.sh
Initial commit
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Makefile
Initial commit
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niosII.qsys
Initial commit
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signal_processing_assignment_defaults.qdf
FPGA programmiert
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signal_processing.cdf
Initial commit
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signal_processing.qpf
Initial commit
2023-10-31 07:47:27 +01:00
signal_processing.qsf
FPGA programmiert
2024-12-18 10:03:57 +01:00
Description
Studentenversion des ESY6/A Praktikums "signal_processing".
11 MiB
Languages
C 42.4%
VHDL 17.9%
Python 10%
Makefile 8.8%
Verilog 6.8%
Other 14.1%