brandlfl78731 118d08219e Versuch 3 CRC, Software fertig

2024-12-04 11:19:36 +01:00

hardware

Versuch 2 Hardware funktioniert

2024-11-27 10:19:31 +01:00

software

Versuch 3 CRC, Software fertig

2024-12-04 11:19:36 +01:00

tests

Versuch 3 CRC, Software fertig

2024-12-04 11:19:36 +01:00

.gitignore

Initial commit

2023-10-31 07:47:27 +01:00

data_channel_hw.tcl

Initial commit

2023-10-31 07:47:27 +01:00

hardware_task_hw.tcl

Initial commit

2023-10-31 07:47:27 +01:00

hardware_timestamp_hw.tcl

Initial commit

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hdl_sources.qsf

Initial commit

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init.sh

Initial commit

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Makefile

Initial commit

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niosII.qsys

Initial commit

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signal_processing.cdf

Initial commit

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signal_processing.qpf

Initial commit

2023-10-31 07:47:27 +01:00

signal_processing.qsf

Initial commit

2023-10-31 07:47:27 +01:00

S

Description

Studentenversion des ESY6/A Praktikums "signal_processing".

11 MiB

Languages

C 42.4%

VHDL 17.9%

Python 10%

Makefile 8.8%

Verilog 6.8%

Other 14.1%