55 lines
1.8 KiB
Plaintext
55 lines
1.8 KiB
Plaintext
# do run.do
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# QuestaSim-64 vlog 2023.2 Compiler 2023.04 Apr 11 2023
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# Start time: 13:15:58 on Apr 29,2026
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# vlog -sv dummz_memgen_16.sv
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# -- Compiling module MemGen_16_10
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#
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# Top level modules:
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# MemGen_16_10
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# End time: 13:15:58 on Apr 29,2026, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2023.2 Compiler 2023.04 Apr 11 2023
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# Start time: 13:15:58 on Apr 29,2026
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# vlog -sv -lint -pedanticerrors -f rtl_flist.f
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# -- Compiling module pc
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# -- Compiling module reg_file
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# -- Compiling module alu
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# -- Compiling module MemGen_32_11
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# -- Compiling module main_mem
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# -- Compiling module decoder
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# -- Compiling module cpu
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#
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# Top level modules:
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# cpu
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# End time: 13:15:58 on Apr 29,2026, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vopt 2023.2 Compiler 2023.04 Apr 11 2023
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# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
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# Start time: 13:15:58 on Apr 29,2026
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# vopt work.cpu -o cpu_opt "+acc" -pedanticerrors
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#
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# Top level modules:
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# cpu
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#
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# Analyzing design...
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# -- Loading module cpu
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# -- Loading module decoder
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# -- Loading module alu
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# -- Loading module reg_file
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# -- Loading module pc
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# -- Loading module main_mem
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# -- Loading module MemGen_32_11
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# -- Loading module MemGen_16_10
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# Optimizing 8 design-units (inlining 0/11 module instances):
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# -- Optimizing module decoder(fast)
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# -- Optimizing module main_mem(fast)
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# -- Optimizing module MemGen_32_11(fast)
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# -- Optimizing module cpu(fast)
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# -- Optimizing module alu(fast)
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# -- Optimizing module MemGen_16_10(fast)
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# -- Optimizing module reg_file(fast)
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# -- Optimizing module pc(fast)
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# Optimized design name is cpu_opt
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# End time: 13:15:58 on Apr 29,2026, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 1
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