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BCDC_RISKV/oasys.log.00
muellerlu fedfd92270 Initial commit
2026-05-29 10:19:13 +02:00

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*******************************************************************
* Oasys-RTL™ - release 2022.2.R1 *
* *
* This material contains trade secrets or otherwise confidential *
* information owned by Siemens Industry Software Inc. or its *
* affiliates (collectively, "SISW"), or its licensors. Access to *
* and use of this information is strictly limited as set forth *
* in the Customer’s applicable agreements with SISW. *
* *
* Unpublished work. © 2023 Siemens *
* *
* Program : ../bin/Linux-x86_64-O/oasysGui *
* Version : 22.2-p002 *
* Date : Mon Jan 16 21:36:23 PST 2023 *
* Build : releases/22.2-54756.0-CentOS_6.5-O *
*******************************************************************
config sdc-v1.7-cpd cli cmd explore mxdb o2n fp rta mpg-m-w dft
loading: oa2tessent-d ctl verify edit bt upf-c aos conc ipc-l vcd o2pp prot int oa2ap
checked out license: psyncore
date : Thu May 28 17:27:15 CEST 2026
ppid/pid : 2483642/2483652
hostname : efiapps0.ads1.fh-nuernberg.de
arch/os : x86_64/Linux-4.18.0-553.123.1.el8_10.x86_64
install : /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1
currdir : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock
logfile : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.log.00
tmpdir : /tmp/oasys.2483642/
> source /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/tcl/library/history.tcl
> source scripts_risc_v/1_read_design.tcl
> source scripts_risc_v/init_design.tcl
> config_shell -echo true
> config_report timing -format {cell edge arrival delay arc_delay net_delay slew net_load load fanout location power_domain}
> source scripts_risc_v/demo_chip_design_files.tcl
-----------------------------
Done setting design variables
-----------------------------
> read_db ./libs/nangate_mvt.odb
info: Reading '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/nangate_mvt.odb' [UFILE-107]
starting at 00:00:00(cpu)/0:01:18(wall) 102MB(vsz)/470MB(peak)
extracting odb ... finished at 00:00:00(cpu)/0:01:18(wall) 102MB(vsz)/470MB(peak)
Write Date : Mon, 21 Jun 2021 13:47:25 -0700
Host : orw-ericc-r78 (64bit)
Tool Version : 21.1-p004 (60,9-71,11)
Tool Date : Fri Jun 11 12:44:10 PDT 2021
Tool Build : 52545.0-O
Design Name :
Comment :
loading environment ... finished at 00:00:00(cpu)/0:01:18(wall) 102MB(vsz)/470MB(peak)
loading libraries ... finished at 00:00:01(cpu)/0:01:18(wall) 114MB(vsz)/476MB(peak)
all done
> create_threshold_voltage_group HVT -lib_cells {NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/ANTENNA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X3_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/HA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC0_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC1_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI33_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI211_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI211_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI211_X4_HVT ...(34 more)}
> create_threshold_voltage_group SVT -lib_cells {NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/ANTENNA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X3_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFRS_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFRS_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFR_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFR_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFS_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLH_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLH_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLL_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLL_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/HA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/LOGIC0_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/LOGIC1_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/MUX2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/MUX2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI33_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI221_X1_SVT ...(34 more)}
> create_threshold_voltage_group LVT -lib_cells {NangateOpenCellLibrary_45nm_LVT_0p85/AND2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND2_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND3_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND3_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND3_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND4_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND4_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND4_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/ANTENNA_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI21_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI21_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI21_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI22_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI22_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI22_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI211_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI211_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI211_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI221_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI221_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI221_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI222_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI222_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI222_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X16_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X32_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKBUF_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKBUF_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKBUF_X3_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFRS_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFRS_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFR_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFR_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFS_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFS_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFF_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFF_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLH_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLH_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLL_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLL_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FA_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X16_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X32_LVT NangateOpenCellLibrary_45nm_LVT_0p85/HA_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X16_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X32_LVT NangateOpenCellLibrary_45nm_LVT_0p85/LOGIC0_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/LOGIC1_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/MUX2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/MUX2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND2_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND3_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND3_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND3_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND4_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND4_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND4_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR2_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR3_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR3_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR3_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR4_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR4_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR4_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI21_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI21_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI21_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI22_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI22_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI22_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI33_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI211_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI211_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI211_X4_LVT ...(34 more)}
> report_operating_conditions
Report Operating conditions:
-----+---------------+--------+-------------+------------------------------------+--------+--------+-----------
|Name |Default?|Type |Library |Process |Voltage |Temperature
-----+---------------+--------+-------------+------------------------------------+--------+--------+-----------
1 |typical | |standard cell|IO |1.000000|1.100000| 27.000000
2 |TYP | |standard cell|PLL_TYP |1.000000|0.900000| 25.000000
3 |typical | |standard cell|MemGen_16_10 |1.000000|1.800000| 25.000000
4 |worst_low_0p85V| |standard cell|NangateOpenCellLibrary_45nm_HVT_0p85|1.000000|0.850000| -40.000000
5 |worst_low | |standard cell|NangateOpenCellLibrary_45nm_HVT |1.000000|0.950000| -40.000000
-----+---------------+--------+-------------+------------------------------------+--------+--------+-----------
> config_tolerance -blackbox true -connection_mismatch true -missing_physical_library true -continue_on_error false
> read_verilog -sv {alu.sv cpu.sv decoder.sv MemGen_32_11.sv main_mem.sv pc.sv reg_file.sv} -include ./riscv_rtl/hw/rtl
info: File 'alu.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/alu.sv' using search_path variable. [CMD-126]
info: File 'cpu.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/cpu.sv' using search_path variable. [CMD-126]
info: File 'decoder.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/decoder.sv' using search_path variable. [CMD-126]
info: File 'MemGen_32_11.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/MemGen_32_11.sv' using search_path variable. [CMD-126]
info: File 'main_mem.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/main_mem.sv' using search_path variable. [CMD-126]
info: File 'pc.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/pc.sv' using search_path variable. [CMD-126]
info: File 'reg_file.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/reg_file.sv' using search_path variable. [CMD-126]
> set_max_route_layer 10
Top-most available layer for routing set to metal10
> set_dont_use {IO/PADBID IO/PADCLK PLL_TYP/PLL MemGen_16_10/MemGen_16_10 NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/ANTENNA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X3_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/HA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC0_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC1_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X4_HVT ...(306 more)} false
-----------------------------
Done preparing design for synthesis
-----------------------------
> source scripts_risc_v/2_synthesize_optimize.tcl
> synthesize -module cpu -map_to_scan
starting synthesize at 00:00:01(cpu)/0:01:24(wall) 120MB(vsz)/480MB(peak)
warning: skipping cell ANTENNA_X1_HVT in the library since it does not have delay arcs [NL-215]
warning: skipping cell FILLCELL_X1_HVT in the library since it does not have delay arcs [NL-215]
warning: skipping cell FILLCELL_X2_HVT in the library since it does not have delay arcs [NL-215]
warning: skipping cell FILLCELL_X4_HVT in the library since it does not have delay arcs [NL-215]
warning: skipping cell FILLCELL_X8_HVT in the library since it does not have delay arcs [NL-215]
warning: skipping cell FILLCELL_X16_HVT in the library since it does not have delay arcs [NL-215]
warning: skipping cell FILLCELL_X32_HVT in the library since it does not have delay arcs [NL-215]
warning: skipping cell LOGIC0_X1_HVT in the library since it does not have delay arcs [NL-215]
warning: skipping cell LOGIC1_X1_HVT in the library since it does not have delay arcs [NL-215]
warning: skipping cell ANTENNA_X1_HVT in the library since it does not have delay arcs [NL-215]
-------> Message [NL-215] suppressed 44 times
info: clock-gating cell for posedge FFs = CLKGATE_X1_LVT in target library 'default' [POWER-112]
info: no clock-gating cell found in target library 'default' for negedge FFs for the given specification [POWER-113]
info: clock_gating minimum_width = 4, maximum_fanout = 2147483647, num_stages = 2147483647, sequential_cell = (null), control_port = (null), control_point = none, observability = no, use_discrete_cells = no, create_multi_stage = no, merge_multi_stage = no, exclude_instantiated_clock_gates = no, log = (null), allow_clock_inversion = no [POWER-111]
info: synthesizing module 'cpu' (depth 1) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/cpu.sv:17)[7]) [VLOG-400]
info: synthesizing module 'decoder' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/decoder.sv:17)[7]) [VLOG-400]
info: synthesizing module 'alu' (depth 3) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/alu.sv:16)[7]) [VLOG-400]
info: done synthesizing module 'alu' (depth 3) (1#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/alu.sv:16)[7]) [VLOG-401]
info: done synthesizing module 'decoder' (depth 2) (2#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/decoder.sv:17)[7]) [VLOG-401]
info: synthesizing module 'reg_file' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/reg_file.sv:15)[7]) [VLOG-400]
warning: target library has multiple operating conditions defined, but no default has been set. Assuming default voltage 0.85V, temperature -40.00 and process 1.00 [LIB-218]
info: done synthesizing module 'reg_file' (depth 2) (3#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/reg_file.sv:15)[7]) [VLOG-401]
info: synthesizing module 'pc' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/pc.sv:16)[7]) [VLOG-400]
info: done synthesizing module 'pc' (depth 2) (4#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/pc.sv:16)[7]) [VLOG-401]
info: synthesizing module 'main_mem' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:18)[7]) [VLOG-400]
info: synthesizing module 'MemGen_32_11' (depth 3) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/MemGen_32_11.sv:1)[7]) [VLOG-400]
info: done synthesizing module 'MemGen_32_11' (depth 3) (5#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/MemGen_32_11.sv:1)[7]) [VLOG-401]
warning: always_comb on 'DRData' did not result in combinational logic ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:110)[8], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:113)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:114)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:118)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:119)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:120)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:121)[17]) [SYN-112]
warning: inferring latch for variable 'DRData' ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:110)[8], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:113)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:114)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:118)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:119)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:120)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:121)[17]) [VLOG-566]
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
-------> Message [POWER-102] suppressed 22 times
info: done synthesizing module 'main_mem' (depth 2) (6#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:18)[7]) [VLOG-401]
info: done synthesizing module 'cpu' (depth 1) (7#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/cpu.sv:17)[7]) [VLOG-401]
finished synthesize at 00:00:02(cpu)/0:01:25(wall) 175MB(vsz)/532MB(peak)
> set_route_layer_max_usage metal2 0.5
> set_route_layer_max_usage metal3 0.8
> set_route_layer_max_usage metal6 0.8
> write_db ./output/odb/riscv_chip.syn.odb
info: design 'cpu' has no physical info [WRITE-120]
warning: WrSdc.. design 'cpu' has no timing constraints [TA-118]
> read_sdc -verbose ./constraints/riscv.sdc
> create_clock -name clk_25mhz -period 40.000 -waveform { 0 20 } clk_25mhz
> set_clock_uncertainty -setup 0.5 clk_25mhz
> set_clock_uncertainty -hold 0.2 clk_25mhz
> set_clock_transition 0.1 clk_25mhz
> set_input_delay -clock clk_25mhz -max 2.0 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] }
> set_input_delay -clock clk_25mhz -min 0.5 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] }
> set_output_delay -clock clk_25mhz -max 2.0 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] }
> set_output_delay -clock clk_25mhz -min 0.5 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] }
> set_false_path -from btn[0]
# set_false_path -from btn[0]
> set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] }
> set_load 0.05 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] }
> current_design
> set_max_fanout 20 cpu
> current_design
> set_max_transition 0.5 cpu
info: 'set_max_fanout' command ignored 1 time(s) [SDC-148]
info: 'set_max_transition' command ignored 1 time(s) [SDC-150]
> report_design_metrics
Report Physical info:
------------------------+--------+-----------+------------
| |Area (squm)|Leakage (uW)
------------------------+--------+-----------+------------
Design Name |cpu | |
Total Instances | 7261| 60155| 625.778
Macros | 4| 46249| 518.216
Pads | 0| 0| 0.000
Phys | 0| 0| 0.000
Blackboxes | 0| 0| 0.000
Cells | 7257| 13906| 107.562
Buffers | 0| 0| 0.000
Inverters | 640| 340| 4.488
Clock-Gates | 31| 107| 0.667
Combinational | 5423| 6454| 51.129
Latches | 32| 85| 0.602
FlipFlops | 1131| 6919| 50.677
Single-Bit FF | 1131| 6919| 50.677
Multi-Bit FF | 0| 0| 0.000
Clock-Gated | 992| |
Bits | 1131| 6919| 50.677
Load-Enabled | 0| |
Clock-Gated | 992| |
Tristate Pin Count | 0| |
Physical Info |Unplaced| |
Chip Size (mm x mm) | | 0|
Fixed Cell Area | | 0|
Phys Only | 0| 0|
Placeable Area | | 0|
Movable Cell Area | | 60155|
Utilization (%) | | |
Chip Utilization (%) | | |
Total Wire Length (mm)| 0.000| |
Longest Wire (mm) | | |
Average Wire (mm) | | |
------------------------+--------+-----------+------------
> check_timing
Report Check Timing:
-----+------------------------------+------+--------+------+-----------------------------------------------
|Item |Errors|Warnings|Status|Description
-----+------------------------------+------+--------+------+-----------------------------------------------
1 |no_clock_defined | 0| 0|Passed|No clock is defined in the design
2 |invalid_generated_clock | 0| 0|Passed|Generated clock is not sourced by a valid clock
3 |unconstrained_IO | 0| 0|Passed|Unconstrained IO pin
4 |unexpected_assertion | 0| 0|Passed|Found unexpected timing assertion
5 |trigger_pin_without_required | 0| 32|Passed|Trigger pin does not get required data
6 |setup_pin_without_data | 0| 0|Passed|Setup pin does not get arriving data
7 |setup_pin_with_clock | 0| 0|Passed|Setup pin has clock signal arriving
8 |clock_pin_with_multiple_clocks| 0| 0|Passed|Clock pin has multiple clock signals
9 |clock_pin_without_clock | 0| 1|Passed|Clock pin does not have clock signal
10 |clock_pin_with_data | 0| 1|Passed|Clock pin has data signal arriving
-----+------------------------------+------+--------+------+-----------------------------------------------
> all_inputs
> group_path -name I2R -from { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] clk_25mhz }
# group_path -from {btn[6]} {btn[5]} {btn[4]} {btn[3]} {btn[2]} {btn[1]} {btn[0]} clk_25mhz
> all_inputs
> all_outputs
> group_path -name I2O -from { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] clk_25mhz } -to { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] }
# group_path -from {btn[6]} {btn[5]} {btn[4]} {btn[3]} {btn[2]} {btn[1]} {btn[0]} clk_25mhz -to {led[7]} {led[6]} {led[5]} {led[4]} {led[3]} {led[2]} {led[1]} {led[0]}
> all_outputs
> group_path -name R2O -to { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] }
# group_path -to {led[7]} {led[6]} {led[5]} {led[4]} {led[3]} {led[2]} {led[1]} {led[0]}
> report_path_groups
Report Path Groups:
-----+-------+------+---------+---------
| Path |Weight|Critical |Worst
| Group | |Range(ps)|Slack(ps)
-----+-------+------+---------+---------
1 |default| 1.000| 0.0| 17832.1
2 |I2R | 1.000| 0.0|<ill>
3 |I2O | 1.000| 0.0|<ill>
4 |R2O | 1.000| 0.0| 36153.7
-----+-------+------+---------+---------
> optimize -virtual
starting optimize at 00:00:03(cpu)/0:01:27(wall) 183MB(vsz)/532MB(peak)
info: mapped 0 flop(s) to scan cells, excluded 0 is_dont_scan flop(s) and 0 is_dont_touch flop(s)
Log file for child PID=2483733: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.00/oasys.w1.00.log
Log file for child PID=2483737: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.00/oasys.w2.00.log
Log file for child PID=2483744: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.00/oasys.w3.00.log
Log file for child PID=2483750: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.00/oasys.w4.00.log
info: optimized '<TOP>' area changed 0.0squm (x1), total 13904.4squm (#1, 0 secs)
info: dissolving instance 'thePC' of module 'pc' in module 'cpu__GC0' [NL-146]
info: optimized 'cpu__GC0' area changed -1457.9squm (x1), total 12446.4squm (#2)
info: optimized 'reg_file__GB1' area changed -841.1squm (x1), total 11605.3squm (#3)
info: optimized 'reg_file__always' area changed -83.5squm (x1), total 11521.8squm (#4)
info: optimized 'main_mem__GC0' area changed -90.4squm (x1), total 11431.3squm (#5)
info: optimized 'MemGen_32_11__block' area changed -2.4squm (x1), total 11429.0squm (#6)
info: optimized '<TOP>' area changed 0.0squm (x1), total 11429.0squm (#7, 0 secs)
info: optimized 'cpu__GC0' area changed 0.0squm (x1), total 11429.0squm (#8)
info: optimized 'MemGen_32_11__block' area changed 0.0squm (x1), total 11429.0squm (#9)
info: optimized '<TOP>' area changed 0.0squm (x1), total 11429.0squm (#10, 0 secs)
done optimizing area at 00:00:15(cpu)/0:01:33(wall) 182MB(vsz)/566MB(peak)
Splitting congested rtl-partitions
info: Target library/cell information has changed that further may change timing results. [TA-159]
info: optimizing design 'cpu' - propagating constants
info: optimized '<TOP>' area changed 0.0squm (x1), total 11429.0squm (#1, 0 secs)
info: set slack mode to optimize shift
info: resetting all path groups
info: activated path group default @ 18015.8ps
info: suspended path group I2R @ <ill>ps
info: suspended path group I2O @ <ill>ps
info: activated path group R2O @ 36338.3ps
info: finished path group default @ 18015.8ps
info: finished path group R2O @ 36338.3ps
info: reactivating path groups
info: reactivated path group default @ 18015.8ps
info: reactivated path group R2O @ 36338.3ps
info: finished path group default @ 18015.8ps
info: finished path group R2O @ 36338.3ps
info: set slack mode to normal
info: done with all path groups
info: restore all path groups
info: starting area recovery on module cpu
info: optimized 'cpu__GC0' area recovered 0.00squm (x1), total 0.00squm (1#5), 0.03 secs
info: optimized 'main_mem__GC0' area recovered 0.00squm (x1), total 0.00squm (2#5), 0.05 secs
info: optimized 'MemGen_32_11__block' area recovered 0.00squm (x1), total 0.00squm (3#5), 0.01 secs
info: optimized 'reg_file__always' area recovered 0.00squm (x1), total 0.00squm (4#5), 0.01 secs
info: optimized 'reg_file__GB1' area recovered 0.00squm (x1), total 0.00squm (5#5), 0.03 secs
info: area recovery done, total area reduction: 0.00squm (0.00%), final slack: 18015.8ps (delta: 0.0ps) (0 secs)
done optimizing virtual at 00:00:16(cpu)/0:01:34(wall) 198MB(vsz)/566MB(peak)
finished optimize at 00:00:16(cpu)/0:01:34(wall) 198MB(vsz)/566MB(peak)
> write_db ./output/odb/riscv_chip.virtual_opt.odb
> report_timing
Report for group default
--------------------------------------------------------------------------------------------------------------------------------------
Startpoint: theMem/IRData_reg[18]/Q
(Clocked by clk_25mhz R)
Endpoint: theMem/mem_addr_reg[5]/D
(Clocked by clk_25mhz F)
Path Group: default
Data required time: 19227.4
(Clock shift: 20000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Setup time: 272.6)
Data arrival time: 1211.5
Slack: 18015.8
Logic depth: 46
--------------------------------------------------------------------------------------------------------------------------------------
Arrival Arc Net Net Total fan-
Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location
(ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um)
--------------------------------------------------------------------------------------------------------------------------------------
clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100
theMem/IRData_reg[18]/CK->Q
SDFF_X1_LVT* rr 84.9 84.9 84.9 0.0 100.0 10.6 73.4 11
theRegisters/i_1_0_1371/A->ZN
INV_X8_LVT rf 87.6 2.7 2.7 0.0 10.2 2.1 13.2 3
theRegisters/i_1_0_1339/A2->ZN
NAND3_X4_LVT fr 101.6 14.0 14.0 0.0 1.0 2.5 17.5 4
theRegisters/i_1_0_1321/A2->ZN
NOR2_X4_LVT* rf 120.6 19.0 19.0 0.0 12.1 29.7 130.1 32
theRegisters/i_1_0_722/B1->ZN
AOI22_X4_LVT* fr 164.9 44.3 44.3 0.0 10.2 0.7 23.4 1
theRegisters/i_1_0_721/A->ZN
INV_X8_LVT rf 167.0 2.1 2.1 0.0 10.2 0.8 3.0 1
theRegisters/i_1_0_718/A->ZN
AOI221_X2_LVT fr 224.3 57.3 57.3 0.0 0.6 0.9 4.4 1
theRegisters/i_1_0_716/A3->ZN
NAND4_X4_LVT rf 239.7 15.4 15.4 0.0 34.6 0.9 3.1 1
theRegisters/i_1_0_715/A->ZN
AOI221_X2_LVT fr 297.1 57.4 57.4 0.0 6.8 0.9 4.3 1
theRegisters/i_1_0_704/A2->ZN
NAND4_X4_LVT rf 317.6 20.5 20.5 0.0 34.4 5.9 16.7 3
theDecoder/i_0_133/C2->ZN
AOI222_X4_LVT fr 428.0 110.5 110.5 0.0 12.2 0.8 23.5 1
theDecoder/i_0_132/A->ZN INV_X32_LVT rf 431.2 3.1 3.1 0.0 10.9 5.4 65.3 7
theDecoder/theALU/i_0_706/B1->ZN
OAI22_X4_LVT* fr 474.4 43.2 43.2 0.0 1.4 1.5 25.9 2
theDecoder/theALU/i_0_705/A->ZN
INV_X8_LVT rf 476.5 2.2 2.2 0.0 10.2 0.6 4.2 1
theDecoder/theALU/i_0_42/A->ZN
OAI21_X2_LVT fr 485.6 9.1 9.1 0.0 0.6 0.8 2.5 1
theDecoder/theALU/i_0_40/C1->ZN
AOI211_X2_LVT rf 491.3 5.6 5.6 0.0 11.6 0.8 2.9 1
theDecoder/theALU/i_0_39/B->ZN
AOI211_X2_LVT fr 538.7 47.4 47.4 0.0 3.3 0.9 3.0 1
theDecoder/theALU/i_0_38/B2->ZN
OAI222_X2_LVT rf 555.6 16.9 16.9 0.0 27.7 0.9 2.9 1
theDecoder/theALU/i_0_37/C2->ZN
AOI221_X2_LVT fr 599.5 43.8 43.8 0.0 8.4 0.9 4.2 1
theDecoder/theALU/i_0_35/B1->ZN
OAI22_X4_LVT* rf 613.4 13.9 13.9 0.0 34.0 0.7 23.4 1
theDecoder/theALU/i_0_34/A->ZN
INV_X8_LVT fr 617.9 4.5 4.5 0.0 10.2 0.6 4.1 1
theDecoder/theALU/i_0_33/A->ZN
AOI21_X4_LVT rf 620.5 2.6 2.6 0.0 2.4 0.8 3.0 1
theDecoder/theALU/i_0_32/C2->ZN
OAI222_X2_LVT fr 659.0 38.5 38.5 0.0 2.6 0.9 3.3 1
theDecoder/theALU/i_0_31/A->ZN
OAI221_X2_LVT rf 675.0 16.0 16.0 0.0 29.2 0.8 4.0 1
theDecoder/theALU/i_0_28/B1->ZN
AOI21_X4_LVT fr 690.5 15.5 15.5 0.0 8.2 0.8 3.0 1
theDecoder/theALU/i_0_27/A->ZN
AOI221_X2_LVT rf 694.7 4.2 4.2 0.0 13.5 0.9 2.9 1
theDecoder/theALU/i_0_26/B->ZN
AOI211_X2_LVT fr 746.9 52.2 52.2 0.0 5.3 0.8 4.6 1
theDecoder/theALU/i_0_25/B2->ZN
OAI22_X2_LVT rf 756.6 9.7 9.7 0.0 31.8 0.8 2.7 1
theDecoder/theALU/i_0_24/C2->ZN
AOI211_X2_LVT fr 791.0 34.4 34.4 0.0 4.0 0.9 3.1 1
theDecoder/theALU/i_0_23/A->ZN
AOI221_X2_LVT rf 796.7 5.8 5.8 0.0 27.8 0.9 3.1 1
theDecoder/theALU/i_0_22/A->ZN
AOI221_X2_LVT fr 850.4 53.7 53.7 0.0 5.4 0.9 3.1 1
theDecoder/theALU/i_0_21/A->ZN
AOI221_X2_LVT rf 856.5 6.1 6.1 0.0 31.2 0.9 3.1 1
theDecoder/theALU/i_0_20/C2->ZN
OAI222_X2_LVT fr 895.2 38.8 38.8 0.0 5.4 0.9 3.3 1
theDecoder/theALU/i_0_19/A->ZN
OAI221_X2_LVT rf 911.8 16.6 16.6 0.0 29.2 0.9 4.7 1
theDecoder/theALU/i_0_18/B2->ZN
AOI22_X4_LVT fr 942.1 30.3 30.3 0.0 8.6 0.8 4.4 1
theDecoder/theALU/i_0_17/B2->ZN
OAI21_X4_LVT rf 948.5 6.4 6.4 0.0 16.9 0.7 4.3 1
theDecoder/theALU/i_0_16/A->ZN
OAI21_X4_LVT fr 958.3 9.8 9.8 0.0 3.6 0.7 3.9 1
theDecoder/theALU/i_0_13/B1->ZN
AOI21_X4_LVT rf 963.5 5.3 5.3 0.0 12.5 0.8 4.4 1
theDecoder/theALU/i_0_12/A4->ZN
NOR4_X2_LVT fr 1020.0 56.5 56.5 0.0 2.9 0.8 2.8 1
theDecoder/theALU/i_0_0/A3->ZN
OR3_X4_LVT rr 1036.6 16.6 16.6 0.0 29.1 0.7 14.7 2
theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1043.2 6.5 6.5 0.0 7.8 0.7 4.3 1
theDecoder/i_0_113/B1->ZN
AOI22_X4_LVT fr 1069.7 26.5 26.5 0.0 5.1 0.8 4.4 1
theDecoder/i_0_111/A2->ZN
AOI22_X4_LVT rf 1076.1 6.4 6.4 0.0 16.9 0.7 4.3 1
theDecoder/i_0_110/A2->ZN
NAND2_X4_LVT* fr 1095.3 19.2 19.2 0.0 4.4 9.0 37.6 13
i_0_0_60/S->Z MUX2_X2_LVT* rf 1161.7 66.4 66.4 0.0 10.2 11.1 66.7 3
theMem/i_0_0_11/B2->ZN AOI22_X4_LVT* fr 1209.5 47.8 47.8 0.0 10.2 0.7 23.4 1
theMem/i_0_0_10/A->ZN INV_X8_LVT rf 1211.5 2.0 2.0 0.0 10.2 0.8 1.8 1
theMem/mem_addr_reg[5]/D SDFF_X1_LVT f 1211.5 0.0 0.0 0.5
--------------------------------------------------------------------------------------------------------------------------------------
Report for group I2R
Report for group I2O
Report for group R2O
--------------------------------------------------------------------------------------------------------------------------------------
Startpoint: theMem/IRData_reg[18]/Q
(Clocked by clk_25mhz R)
Endpoint: led[7]
(Clocked by clk_25mhz R)
Path Group: R2O
Data required time: 37500.0
(Clock shift: 40000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Out delay: 2000.0)
Data arrival time: 1161.7
Slack: 36338.3
Logic depth: 44
--------------------------------------------------------------------------------------------------------------------------------------
Arrival Arc Net Net Total fan-
Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location
(ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um)
--------------------------------------------------------------------------------------------------------------------------------------
clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100
theMem/IRData_reg[18]/CK->Q
SDFF_X1_LVT* rr 84.9 84.9 84.9 0.0 100.0 10.6 73.4 11
theRegisters/i_1_0_1371/A->ZN
INV_X8_LVT rf 87.6 2.7 2.7 0.0 10.2 2.1 13.2 3
theRegisters/i_1_0_1339/A2->ZN
NAND3_X4_LVT fr 101.6 14.0 14.0 0.0 1.0 2.5 17.5 4
theRegisters/i_1_0_1321/A2->ZN
NOR2_X4_LVT* rf 120.6 19.0 19.0 0.0 12.1 29.7 130.1 32
theRegisters/i_1_0_722/B1->ZN
AOI22_X4_LVT* fr 164.9 44.3 44.3 0.0 10.2 0.7 23.4 1
theRegisters/i_1_0_721/A->ZN
INV_X8_LVT rf 167.0 2.1 2.1 0.0 10.2 0.8 3.0 1
theRegisters/i_1_0_718/A->ZN
AOI221_X2_LVT fr 224.3 57.3 57.3 0.0 0.6 0.9 4.4 1
theRegisters/i_1_0_716/A3->ZN
NAND4_X4_LVT rf 239.7 15.4 15.4 0.0 34.6 0.9 3.1 1
theRegisters/i_1_0_715/A->ZN
AOI221_X2_LVT fr 297.1 57.4 57.4 0.0 6.8 0.9 4.3 1
theRegisters/i_1_0_704/A2->ZN
NAND4_X4_LVT rf 317.6 20.5 20.5 0.0 34.4 5.9 16.7 3
theDecoder/i_0_133/C2->ZN
AOI222_X4_LVT fr 428.0 110.5 110.5 0.0 12.2 0.8 23.5 1
theDecoder/i_0_132/A->ZN INV_X32_LVT rf 431.2 3.1 3.1 0.0 10.9 5.4 65.3 7
theDecoder/theALU/i_0_706/B1->ZN
OAI22_X4_LVT* fr 474.4 43.2 43.2 0.0 1.4 1.5 25.9 2
theDecoder/theALU/i_0_705/A->ZN
INV_X8_LVT rf 476.5 2.2 2.2 0.0 10.2 0.6 4.2 1
theDecoder/theALU/i_0_42/A->ZN
OAI21_X2_LVT fr 485.6 9.1 9.1 0.0 0.6 0.8 2.5 1
theDecoder/theALU/i_0_40/C1->ZN
AOI211_X2_LVT rf 491.3 5.6 5.6 0.0 11.6 0.8 2.9 1
theDecoder/theALU/i_0_39/B->ZN
AOI211_X2_LVT fr 538.7 47.4 47.4 0.0 3.3 0.9 3.0 1
theDecoder/theALU/i_0_38/B2->ZN
OAI222_X2_LVT rf 555.6 16.9 16.9 0.0 27.7 0.9 2.9 1
theDecoder/theALU/i_0_37/C2->ZN
AOI221_X2_LVT fr 599.5 43.8 43.8 0.0 8.4 0.9 4.2 1
theDecoder/theALU/i_0_35/B1->ZN
OAI22_X4_LVT* rf 613.4 13.9 13.9 0.0 34.0 0.7 23.4 1
theDecoder/theALU/i_0_34/A->ZN
INV_X8_LVT fr 617.9 4.5 4.5 0.0 10.2 0.6 4.1 1
theDecoder/theALU/i_0_33/A->ZN
AOI21_X4_LVT rf 620.5 2.6 2.6 0.0 2.4 0.8 3.0 1
theDecoder/theALU/i_0_32/C2->ZN
OAI222_X2_LVT fr 659.0 38.5 38.5 0.0 2.6 0.9 3.3 1
theDecoder/theALU/i_0_31/A->ZN
OAI221_X2_LVT rf 675.0 16.0 16.0 0.0 29.2 0.8 4.0 1
theDecoder/theALU/i_0_28/B1->ZN
AOI21_X4_LVT fr 690.5 15.5 15.5 0.0 8.2 0.8 3.0 1
theDecoder/theALU/i_0_27/A->ZN
AOI221_X2_LVT rf 694.7 4.2 4.2 0.0 13.5 0.9 2.9 1
theDecoder/theALU/i_0_26/B->ZN
AOI211_X2_LVT fr 746.9 52.2 52.2 0.0 5.3 0.8 4.6 1
theDecoder/theALU/i_0_25/B2->ZN
OAI22_X2_LVT rf 756.6 9.7 9.7 0.0 31.8 0.8 2.7 1
theDecoder/theALU/i_0_24/C2->ZN
AOI211_X2_LVT fr 791.0 34.4 34.4 0.0 4.0 0.9 3.1 1
theDecoder/theALU/i_0_23/A->ZN
AOI221_X2_LVT rf 796.7 5.8 5.8 0.0 27.8 0.9 3.1 1
theDecoder/theALU/i_0_22/A->ZN
AOI221_X2_LVT fr 850.4 53.7 53.7 0.0 5.4 0.9 3.1 1
theDecoder/theALU/i_0_21/A->ZN
AOI221_X2_LVT rf 856.5 6.1 6.1 0.0 31.2 0.9 3.1 1
theDecoder/theALU/i_0_20/C2->ZN
OAI222_X2_LVT fr 895.2 38.8 38.8 0.0 5.4 0.9 3.3 1
theDecoder/theALU/i_0_19/A->ZN
OAI221_X2_LVT rf 911.8 16.6 16.6 0.0 29.2 0.9 4.7 1
theDecoder/theALU/i_0_18/B2->ZN
AOI22_X4_LVT fr 942.1 30.3 30.3 0.0 8.6 0.8 4.4 1
theDecoder/theALU/i_0_17/B2->ZN
OAI21_X4_LVT rf 948.5 6.4 6.4 0.0 16.9 0.7 4.3 1
theDecoder/theALU/i_0_16/A->ZN
OAI21_X4_LVT fr 958.3 9.8 9.8 0.0 3.6 0.7 3.9 1
theDecoder/theALU/i_0_13/B1->ZN
AOI21_X4_LVT rf 963.5 5.3 5.3 0.0 12.5 0.8 4.4 1
theDecoder/theALU/i_0_12/A4->ZN
NOR4_X2_LVT fr 1020.0 56.5 56.5 0.0 2.9 0.8 2.8 1
theDecoder/theALU/i_0_0/A3->ZN
OR3_X4_LVT rr 1036.6 16.6 16.6 0.0 29.1 0.7 14.7 2
theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1043.2 6.5 6.5 0.0 7.8 0.7 4.3 1
theDecoder/i_0_113/B1->ZN
AOI22_X4_LVT fr 1069.7 26.5 26.5 0.0 5.1 0.8 4.4 1
theDecoder/i_0_111/A2->ZN
AOI22_X4_LVT rf 1076.1 6.4 6.4 0.0 16.9 0.7 4.3 1
theDecoder/i_0_110/A2->ZN
NAND2_X4_LVT* fr 1095.3 19.2 19.2 0.0 4.4 9.0 37.6 13
i_0_0_60/S->Z MUX2_X2_LVT* rf 1161.7 66.4 66.4 0.0 10.2 11.1 66.7 3
led[7] f 1161.7 0.0 0.0 10.2
--------------------------------------------------------------------------------------------------------------------------------------
> report_path_groups
Report Path Groups:
-----+-------+------+---------+---------
| Path |Weight|Critical |Worst
| Group | |Range(ps)|Slack(ps)
-----+-------+------+---------+---------
1 |default| 1.000| 0.0| 18015.8
2 |I2R | 1.000| 0.0|<ill>
3 |I2O | 1.000| 0.0|<ill>
4 |R2O | 1.000| 0.0| 36338.3
-----+-------+------+---------+---------
-------------------------------------
Synthesis and optimization complete
-------------------------------------
INFO::Running oasys Tessent DFT flow
> source scripts_risc_v/oasys_tessent_dft.tcl
INFO::using /applications/SiemensEDA/siemenseda2023/tessent/bin/tessent build to run the Tessent DFT flow
> config_tessent -exec_path /applications/SiemensEDA/siemenseda2023/tessent/bin/tessent
> define_test_clock -pin clk_25mhz
> define_test_pin -pin scan_en -scan_mode 1 -default_scan_enable -create_port
Adding Test pin scan_en to top Module
> set_dont_scan theMem true
> define_test_pin -name reset -pin {btn[0]} -scan_mode 1
> check_dft -auto_test_clock -auto_test_pins
starting check_dft at 00:00:16(cpu)/0:01:35(wall) 198MB(vsz)/566MB(peak)
Checking DFT rules for 'cpu'
Running DFT TDRC iteration 1
Total 1131 scanModels/flops with 12% scanable (139 pass, 992 fail, 0 nonScan or excludeScan)
Report Check DFT:
-----+---------------------+------+--------+------+-------------------------------------------
|Item |Errors|Warnings|Status|Description
-----+---------------------+------+--------+------+-------------------------------------------
1 |internal_clock | 0| 0|Passed|Internal Clock
2 |constant_clock | 0| 0|Passed|Constant Clock
3 |non_clock_PI | 0| 0|Passed|Non-Clock PI
4 |blocking_clock_gate | 0| 31|Failed|Blocking clock gate
5 |internal_async | 0| 0|Passed|Internal Async. Set/Reset control
6 |constant_active_async| 0| 0|Passed|Constant active Async. Set/Reset signal
7 |non_test_PI | 0| 0|Passed|Unconstrained PI driving Async/ Set/Reset
8 |async_clock_conflict | 0| 0|Passed|Async. Set/Reset signal and Clock conflict
9 |parallel_scan_clock | 0| 0|Passed|Clock pin of unsupported parallel-scan flop
-----+---------------------+------+--------+------+-------------------------------------------
Design has 31 DFT violation(s)
finished check_dft at 00:00:17(cpu)/0:01:35(wall) 198MB(vsz)/566MB(peak)
> write_db ./output/odb/riscv.tessent_pre_fix.odb
> fix_dft_violations -type all -test_clock clk_25mhz -test_control scan_en
Created 0 gates to fix Async violation(s)
Created 0 muxes to fix clock violation(s)
Replaced 31 clock-gating cells to fix clock-gating violation(s)
> report_dft_violations
Report DftViolations:
-----+-------------------+-----------------------------------------------+--------------------
| Type | Pin | Affected Registers
-----+-------------------+-----------------------------------------------+--------------------
1 |blocking clock gate|theRegisters/clk_gate_registers_reg[1]_reg/GCK | 32
2 |blocking clock gate|theRegisters/clk_gate_registers_reg[2]_reg/GCK | 32
3 |blocking clock gate|theRegisters/clk_gate_registers_reg[3]_reg/GCK | 32
4 |blocking clock gate|theRegisters/clk_gate_registers_reg[4]_reg/GCK | 32
5 |blocking clock gate|theRegisters/clk_gate_registers_reg[5]_reg/GCK | 32
6 |blocking clock gate|theRegisters/clk_gate_registers_reg[6]_reg/GCK | 32
7 |blocking clock gate|theRegisters/clk_gate_registers_reg[7]_reg/GCK | 32
8 |blocking clock gate|theRegisters/clk_gate_registers_reg[8]_reg/GCK | 32
9 |blocking clock gate|theRegisters/clk_gate_registers_reg[9]_reg/GCK | 32
10 |blocking clock gate|theRegisters/clk_gate_registers_reg[10]_reg/GCK| 32
11 |blocking clock gate|theRegisters/clk_gate_registers_reg[11]_reg/GCK| 32
12 |blocking clock gate|theRegisters/clk_gate_registers_reg[12]_reg/GCK| 32
13 |blocking clock gate|theRegisters/clk_gate_registers_reg[13]_reg/GCK| 32
14 |blocking clock gate|theRegisters/clk_gate_registers_reg[14]_reg/GCK| 32
15 |blocking clock gate|theRegisters/clk_gate_registers_reg[15]_reg/GCK| 32
16 |blocking clock gate|theRegisters/clk_gate_registers_reg[16]_reg/GCK| 32
17 |blocking clock gate|theRegisters/clk_gate_registers_reg[17]_reg/GCK| 32
18 |blocking clock gate|theRegisters/clk_gate_registers_reg[18]_reg/GCK| 32
19 |blocking clock gate|theRegisters/clk_gate_registers_reg[19]_reg/GCK| 32
20 |blocking clock gate|theRegisters/clk_gate_registers_reg[20]_reg/GCK| 32
21 |blocking clock gate|theRegisters/clk_gate_registers_reg[21]_reg/GCK| 32
22 |blocking clock gate|theRegisters/clk_gate_registers_reg[22]_reg/GCK| 32
23 |blocking clock gate|theRegisters/clk_gate_registers_reg[23]_reg/GCK| 32
24 |blocking clock gate|theRegisters/clk_gate_registers_reg[24]_reg/GCK| 32
25 |blocking clock gate|theRegisters/clk_gate_registers_reg[25]_reg/GCK| 32
26 |blocking clock gate|theRegisters/clk_gate_registers_reg[26]_reg/GCK| 32
27 |blocking clock gate|theRegisters/clk_gate_registers_reg[27]_reg/GCK| 32
28 |blocking clock gate|theRegisters/clk_gate_registers_reg[28]_reg/GCK| 32
29 |blocking clock gate|theRegisters/clk_gate_registers_reg[29]_reg/GCK| 32
30 |blocking clock gate|theRegisters/clk_gate_registers_reg[30]_reg/GCK| 32
31 |blocking clock gate|theRegisters/clk_gate_registers_reg[31]_reg/GCK| 32
-----+-------------------+-----------------------------------------------+--------------------
> optimize
starting optimize at 00:00:17(cpu)/0:01:36(wall) 198MB(vsz)/566MB(peak)
info: mapped 107 flop(s) to scan cells, excluded 107 is_dont_scan flop(s) and 0 is_dont_touch flop(s)
info: Target library/cell information has changed that further may change timing results. [TA-159]
info: optimizing design 'cpu' - propagating constants
info: optimized '<TOP>' area changed 0.0squm (x1), total 11274.7squm (#1, 0 secs)
info: set slack mode to optimize shift
info: resetting all path groups
info: activated path group default @ 18139.2ps
info: suspended path group I2R @ <ill>ps
info: suspended path group I2O @ <ill>ps
info: activated path group R2O @ 36317.8ps
info: finished path group default @ 18139.2ps
info: finished path group R2O @ 36317.8ps
info: reactivating path groups
info: reactivated path group default @ 18139.2ps
info: reactivated path group R2O @ 36317.8ps
info: finished path group default @ 18139.2ps
info: finished path group R2O @ 36317.8ps
info: set slack mode to normal
info: done with all path groups
info: restore all path groups
info: starting area recovery on module cpu
info: optimized 'cpu__GC0' area recovered 0.00squm (x1), total 0.00squm (1#5), 0.04 secs
info: optimized 'main_mem__GC0' area recovered 0.00squm (x1), total 0.00squm (2#5), 0.04 secs
info: optimized 'MemGen_32_11__block' area recovered 0.00squm (x1), total 0.00squm (3#5), 0.00 secs
info: optimized 'reg_file__always' area recovered 0.00squm (x1), total 0.00squm (4#5), 0.01 secs
info: optimized 'reg_file__GB1' area recovered 0.00squm (x1), total 0.00squm (5#5), 0.02 secs
info: area recovery done, total area reduction: 0.00squm (0.00%), final slack: 18139.2ps (delta: 0.0ps) (0 secs)
done optimizing virtual at 00:00:18(cpu)/0:01:37(wall) 203MB(vsz)/566MB(peak)
info: floorplan : total 4 movable macros and 0 fixed macros
info: creating tracks for 10 routing layers [FP-148]
info: start floorplan stage 0 [FP-145]
info: end floorplan stage 0 [FP-145]
info: start floorplan stage 1 [FP-145]
info: end floorplan stage 1 [FP-145]
info: start rtl partition placement [PLACE-114]
info: placement mode : raw [PLACE-115]
info: set slack mode to weight modified
info: set slack mode to normal
info: set slack mode to optimize shift
info: timing-driven placement : ON [PLACE-116]
info: congestion-driven placement : ON [PLACE-117]
info: placement movable objects : macros 0 , rtl partitions 5, cells 0 [PLACE-118]
info: start placement stage 0 [PLACE-111]
info: end placement stage 0 [PLACE-111]
info: set slack mode to normal
info: cell density map (bin size 20 x 20 rows), maximum utilization: 170.00% average utilization: 13.98% [PLACE-153]
info: 9.00% bins with overflow, average overflow 18.49% [PLACE-154]
info: P-D: 0.090% (0.185 ~ 0.700)
Total Wire Length = 77698.10
Average Wire = 58.60
Longest Wire = 352.69
Shortest Wire = 0.00
WNS = 18139.5ps
info: placing 17 unplaced IO Pins
info: start rtl partition placement [PLACE-114]
info: placement mode : raw [PLACE-115]
info: set slack mode to weight modified
info: set slack mode to normal
info: set slack mode to optimize shift
info: timing-driven placement : ON [PLACE-116]
info: congestion-driven placement : ON [PLACE-117]
info: placement movable objects : macros 0 , rtl partitions 5, cells 0 [PLACE-118]
info: start placement stage 0 [PLACE-111]
info: end placement stage 0 [PLACE-111]
info: set slack mode to normal
info: cell density map (bin size 20 x 20 rows), maximum utilization: 90.53% average utilization: 14.23% [PLACE-153]
info: 0.00% bins with overflow, average overflow 0.00% [PLACE-154]
info: P-D: 0.000% (0.000 ~ 0.000)
Total Wire Length = 115431.45
Average Wire = 87.05
Longest Wire = 426.66
Shortest Wire = 10.50
WNS = 18131.2ps
info: 0 power/ground pre-route segments processed. [PLACE-144]
info: 0 routing blockages processed. [PLACE-145]
info: replaced @ 18131.2ps
done optimize placement at 00:00:21(cpu)/0:01:39(wall) 404MB(vsz)/822MB(peak)
info: cell density map (bin size 20 x 20 rows), maximum utilization: 90.53% average utilization: 14.23% [PLACE-153]
info: 0.00% bins with overflow, average overflow 0.00% [PLACE-154]
info: set slack mode to optimize shift
info: resetting all path groups
info: activated path group default @ 18131.2ps
info: suspended path group I2R @ <ill>ps
info: suspended path group I2O @ <ill>ps
info: activated path group R2O @ 36309.8ps
info: finished path group default @ 18131.2ps
info: finished path group R2O @ 36309.8ps
info: reactivating path groups
info: reactivated path group default @ 18131.2ps
info: reactivated path group R2O @ 36309.8ps
info: finished path group default @ 18131.2ps
info: finished path group R2O @ 36309.8ps
info: cell density map (bin size 20 x 20 rows), maximum utilization: 90.53% average utilization: 14.23% [PLACE-153]
info: 0.00% bins with overflow, average overflow 0.00% [PLACE-154]
info: 0 power/ground pre-route segments processed. [PLACE-144]
info: 0 routing blockages processed. [PLACE-145]
info: set slack mode to normal
info: done with all path groups
info: restore all path groups
info: (0) optimizing 'theMem/i_0/IAddr[5]' (path group default) @ 18131.2ps(1/1) (4 secs)
finished optimize at 00:00:21(cpu)/0:01:39(wall) 404MB(vsz)/822MB(peak)
> write_db ./output/odb/riscv.tessent_post_fix.odb
> write_verilog ./output/riscv.tessent_post_fix.v
info: writing Verilog file './output/riscv.tessent_post_fix.v' for module 'cpu' [WRITE-100]
> config_tessent -library {./libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib ./libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib ./libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib ./libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib ./libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib ./libs/fastscan/PLL.fslib ./libs/fastscan/IO.fslib}
--------------check dft---------------
> check_dft
starting check_dft at 00:00:22(cpu)/0:01:40(wall) 395MB(vsz)/822MB(peak)
Checking DFT rules for 'cpu'
Running DFT TDRC iteration 1
Total 1131 scanModels/flops with 90% scanable (1024 pass, 0 fail, 107 nonScan or excludeScan)
Report Check DFT:
-----+---------------------+------+--------+------+-------------------------------------------
|Item |Errors|Warnings|Status|Description
-----+---------------------+------+--------+------+-------------------------------------------
1 |internal_clock | 0| 0|Passed|Internal Clock
2 |constant_clock | 0| 0|Passed|Constant Clock
3 |non_clock_PI | 0| 0|Passed|Non-Clock PI
4 |blocking_clock_gate | 0| 0|Passed|Blocking clock gate
5 |internal_async | 0| 0|Passed|Internal Async. Set/Reset control
6 |constant_active_async| 0| 0|Passed|Constant active Async. Set/Reset signal
7 |non_test_PI | 0| 0|Passed|Unconstrained PI driving Async/ Set/Reset
8 |async_clock_conflict | 0| 0|Passed|Async. Set/Reset signal and Clock conflict
9 |parallel_scan_clock | 0| 0|Passed|Clock pin of unsupported parallel-scan flop
-----+---------------------+------+--------+------+-------------------------------------------
Design has 0 DFT violation(s)
finished check_dft at 00:00:22(cpu)/0:01:40(wall) 395MB(vsz)/822MB(peak)
--------------define Scan-Chains---------------
> define_scan_chain -scan_in SI_1 -scan_out SO_1 -create_port
Defining Scan Chain scanChain_1( si:SI_1, so:SO_1)
Adding Scan-in pin SI_1 to top Module
Adding Scan-out pin SO_1 to top Module
> define_scan_chain -scan_in SI_2 -scan_out SO_2 -create_port
Defining Scan Chain scanChain_2( si:SI_2, so:SO_2)
Adding Scan-in pin SI_2 to top Module
Adding Scan-out pin SO_2 to top Module
> define_scan_chain -scan_in SI_3 -scan_out SO_3 -create_port
Defining Scan Chain scanChain_3( si:SI_3, so:SO_3)
Adding Scan-in pin SI_3 to top Module
Adding Scan-out pin SO_3 to top Module
> define_scan_chain -scan_in SI_4 -scan_out SO_4 -create_port
Defining Scan Chain scanChain_4( si:SI_4, so:SO_4)
Adding Scan-in pin SI_4 to top Module
Adding Scan-out pin SO_4 to top Module
----------run_tessent_scan----------------
> run_tessent_scan
info: writing Verilog file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys_netlist.v' for module 'cpu' [WRITE-100]
starting check_dft at 00:00:22(cpu)/0:01:40(wall) 395MB(vsz)/822MB(peak)
Checking DFT rules for 'cpu'
Running DFT TDRC iteration 1
Total 1131 scanModels/flops with 90% scanable (1024 pass, 0 fail, 107 nonScan or excludeScan)
Report Check DFT:
-----+---------------------+------+--------+------+-------------------------------------------
|Item |Errors|Warnings|Status|Description
-----+---------------------+------+--------+------+-------------------------------------------
1 |internal_clock | 0| 0|Passed|Internal Clock
2 |constant_clock | 0| 0|Passed|Constant Clock
3 |non_clock_PI | 0| 0|Passed|Non-Clock PI
4 |blocking_clock_gate | 0| 0|Passed|Blocking clock gate
5 |internal_async | 0| 0|Passed|Internal Async. Set/Reset control
6 |constant_active_async| 0| 0|Passed|Constant active Async. Set/Reset signal
7 |non_test_PI | 0| 0|Passed|Unconstrained PI driving Async/ Set/Reset
8 |async_clock_conflict | 0| 0|Passed|Async. Set/Reset signal and Clock conflict
9 |parallel_scan_clock | 0| 0|Passed|Clock pin of unsupported parallel-scan flop
-----+---------------------+------+--------+------+-------------------------------------------
Design has 0 DFT violation(s)
finished check_dft at 00:00:22(cpu)/0:01:40(wall) 395MB(vsz)/822MB(peak)
Configuring 4 scan chain(s)
Configuring DEFAULT DFT partition
Enabling physical aware scan chains
Configuring 4 scan chain(s) for 1024 scan instance(s) in 1 test clock domain(s)
Domain clk_25mhz has 1024 flop(s) (1024 rise, 0 fall), 4 chain(s) (4,0)
Assigning chain scanChain_1 to domain clk_25mhz (edge: rise) (capacity: 256)
Assigning chain scanChain_2 to domain clk_25mhz (edge: rise) (capacity: 256)
Assigning chain scanChain_3 to domain clk_25mhz (edge: rise) (capacity: 256)
Assigning chain scanChain_4 to domain clk_25mhz (edge: rise) (capacity: 256)
info: writing Sdc file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys.sdc' for design 'cpu' [WRITE-104]
info: Parameter 'tessentScandefFilePath' set to '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/cpu.scandef' [PARAM-104]
**************************************************************************************************************************************************************************************
TESSENT EXECUTION BEGINS
Invoking Tessent Executable : /applications/SiemensEDA/siemenseda2023/tessent_2023.4-p1/bin/tessent
DoFile : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/scan.do
**************************************************************************************************************************************************************************************
/applications/SiemensEDA/siemenseda2023/tessent_2023.4-p1/bin/tessent -shell -dofile /tmp/oasys.2483642/.tmpTessentFile -log_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/scan.log -replace
// Tessent Shell 2023.4-p1 Mon Feb 19 16:22:02 GMT 2024
// Unpublished work. Copyright 2024 Siemens
//
// This material contains trade secrets or otherwise confidential
// information owned by Siemens Industry Software Inc. or its affiliates
// (collectively, "SISW"), or its licensors. Access to and use of this
// information is strictly limited as set forth in the Customer's
// applicable agreements with SISW.
//
// Siemens software executing under x86-64 Linux on Thu May 28 17:28:57 CEST 2026.
// 64 bit version
// Host: efiapps0.ads1.fh-nuernberg.de (12 x 3.5 GHz, 48014 MB RAM, 24575 MB Swap)
//
// command: if {[catch {source /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/scan.do} msg]} {
// puts "$msg"
// puts "TESSENT_ER_ORTL" }
// sub-command: set_context dft -scan -no_rtl -design_id Scan_0
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib
// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib
// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib
// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib
// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+} -regexp -append
// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[A-Z]+} -regexp -append
// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+[_]+[A-Z]+} -regexp -append
// sub-command: read_verilog /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys_netlist.v
// sub-command: set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/tsdb_outdir
// sub-command: read_sdc /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys.sdc
// Command 'read_sdc' requires an elaborated design. Automatically elaborating the design ...
// Note: 640 duplicate cell library models were read. The last model read of the same name was kept.
// To see detailed messages per duplicate model, issue 'set_cell_library_options -report_duplicate_models on'
// before issuing 'read_cell_library'.
// Warning: 1 cell library model contained 2 floating model outputs.
// To see detailed messages per model, issue 'set_cell_library_options -report_floating_nets on'
// before issuing 'read_cell_library'.
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X1' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X2' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X4' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X8' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X1_HVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X2_HVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X4_HVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X8_HVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X1_SVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X2_SVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X4_SVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X8_SVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X1_LVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X2_LVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X4_LVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib'
// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
// Model 'CLKGATE_X8_LVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib'
// Note: Top design is 'cpu'.
// Warning: Undefined modules were found.
// Before using "set_system_mode" or "create_flat_model", you must either define
// the missing modules using "read_verilog" and/or "read_cell_library", or use the
// following command to treat them as black boxes:
add_black_boxes -modules { \
MemGen_16_10 \
}
// You can also use "add_black_boxes -auto" to black box all undefined modules but
// it is recommended that you do not add this command to your dofile. Doing so may
// unintentionally black-box new undefined modules in future runs.
// Warning: 32 cases: Unused net in DFT library model
// Warning: 110 cases: Undriven net in netlist module
// Warning: 1 case: Floating input on instance in netlist
// Warning: 47 cases: Net in netlist not connected
// Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings
// Design elaboration successful.
// Reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys.sdc ...
// Finished reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys.sdc.
// Read SDC summary: 1 false path, 0 multi-cycle paths, 0 erroneous paths
// 0 disable timings, 0 case analysis, 0 clock groups
// sub-command: set_current_design cpu -show_elaboration_warnings
// Warning: Undefined modules were found.
// Before using "set_system_mode" or "create_flat_model", you must either define
// the missing modules using "read_verilog" and/or "read_cell_library", or use the
// following command to treat them as black boxes:
add_black_boxes -modules { \
MemGen_16_10 \
}
// You can also use "add_black_boxes -auto" to black box all undefined modules but
// it is recommended that you do not add this command to your dofile. Doing so may
// unintentionally black-box new undefined modules in future runs.
// Warning: Net 'SO_1' in module 'cpu' is not driven
// Warning: Net 'SO_2' in module 'cpu' is not driven
// Warning: Net 'SO_3' in module 'cpu' is not driven
// Warning: Net 'SO_4' in module 'cpu' is not driven
// Warning: Net 'DAddr[31]' in module 'cpu' has no pins
// Warning: Net 'DAddr[30]' in module 'cpu' has no pins
// Warning: Net 'DAddr[29]' in module 'cpu' has no pins
// Warning: Net 'DAddr[28]' in module 'cpu' has no pins
// Warning: Net 'DAddr[27]' in module 'cpu' has no pins
// Warning: Net 'DAddr[26]' in module 'cpu' has no pins
// Warning: Net 'DAddr[25]' in module 'cpu' has no pins
// Warning: Net 'DAddr[24]' in module 'cpu' has no pins
// Warning: Net 'DAddr[23]' in module 'cpu' has no pins
// Warning: Net 'DAddr[22]' in module 'cpu' has no pins
// Warning: Net 'DAddr[21]' in module 'cpu' has no pins
// Warning: Net 'DAddr[20]' in module 'cpu' has no pins
// Warning: Net 'DAddr[19]' in module 'cpu' has no pins
// Warning: Net 'DAddr[18]' in module 'cpu' has no pins
// Warning: Net 'DAddr[17]' in module 'cpu' has no pins
// Warning: Net 'DAddr[16]' in module 'cpu' has no pins
// Warning: Net 'DAddr[15]' in module 'cpu' has no pins
// Warning: Net 'DAddr[14]' in module 'cpu' has no pins
// Warning: Net 'DAddr[13]' in module 'cpu' has no pins
// Warning: Net 'NextPC[31]' in module 'cpu' has no pins
// Warning: Net 'NextPC[30]' in module 'cpu' has no pins
// Warning: Net 'NextPC[29]' in module 'cpu' has no pins
// Warning: Net 'NextPC[28]' in module 'cpu' has no pins
// Warning: Net 'NextPC[27]' in module 'cpu' has no pins
// Warning: Net 'NextPC[26]' in module 'cpu' has no pins
// Warning: Net 'NextPC[25]' in module 'cpu' has no pins
// Warning: Net 'NextPC[24]' in module 'cpu' has no pins
// Warning: Net 'NextPC[23]' in module 'cpu' has no pins
// Warning: Net 'NextPC[22]' in module 'cpu' has no pins
// Warning: Net 'NextPC[21]' in module 'cpu' has no pins
// Warning: Net 'NextPC[20]' in module 'cpu' has no pins
// Warning: Net 'NextPC[19]' in module 'cpu' has no pins
// Warning: Net 'NextPC[18]' in module 'cpu' has no pins
// Warning: Net 'NextPC[17]' in module 'cpu' has no pins
// Warning: Net 'NextPC[16]' in module 'cpu' has no pins
// Warning: Net 'NextPC[15]' in module 'cpu' has no pins
// Warning: Net 'NextPC[14]' in module 'cpu' has no pins
// Warning: Net 'NextPC[13]' in module 'cpu' has no pins
// Warning: Net 'NextPC[7]' in module 'cpu' has no pins
// Warning: Net 'NextPC[6]' in module 'cpu' has no pins
// Warning: Net 'NextPC[5]' in module 'cpu' has no pins
// Warning: Net 'NextPC[4]' in module 'cpu' has no pins
// Warning: Net 'NextPC[3]' in module 'cpu' has no pins
// Warning: Net 'NextPC[2]' in module 'cpu' has no pins
// Warning: Net 'NextPC[1]' in module 'cpu' has no pins
// Warning: Net 'NextPC[0]' in module 'cpu' has no pins
// Warning: Net 'uc_0' in module 'cpu' is not driven
// Warning: Net 'uc_1' in module 'cpu' is not driven
// Warning: Net 'uc_2' in module 'cpu' is not driven
// Warning: Net 'uc_3' in module 'cpu' is not driven
// Warning: Net 'uc_4' in module 'cpu' is not driven
// Warning: Net 'uc_5' in module 'cpu' is not driven
// Warning: Net 'uc_6' in module 'cpu' is not driven
// Warning: Net 'uc_7' in module 'cpu' is not driven
// Warning: Net 'uc_8' in module 'cpu' is not driven
// Warning: Net 'uc_9' in module 'cpu' is not driven
// Warning: Net 'uc_10' in module 'cpu' is not driven
// Warning: Net 'uc_11' in module 'cpu' is not driven
// Warning: Net 'uc_12' in module 'cpu' is not driven
// Warning: Net 'uc_13' in module 'cpu' is not driven
// Warning: Net 'uc_14' in module 'cpu' is not driven
// Warning: Net 'uc_15' in module 'cpu' is not driven
// Warning: Net 'uc_16' in module 'cpu' is not driven
// Warning: Net 'uc_17' in module 'cpu' is not driven
// Warning: Net 'uc_18' in module 'cpu' is not driven
// Warning: Net 'uc_19' in module 'cpu' is not driven
// Warning: Net 'uc_20' in module 'cpu' is not driven
// Warning: Net 'uc_21' in module 'cpu' is not driven
// Warning: Net 'uc_22' in module 'cpu' is not driven
// Warning: Net 'uc_23' in module 'cpu' is not driven
// Warning: Net 'uc_24' in module 'cpu' is not driven
// Warning: Net 'uc_25' in module 'cpu' is not driven
// Warning: Net 'uc_26' in module 'cpu' is not driven
// Warning: Net 'uc_27' in module 'cpu' is not driven
// Warning: Net 'uc_28' in module 'cpu' is not driven
// Warning: Net 'uc_29' in module 'cpu' is not driven
// Warning: Net 'uc_30' in module 'cpu' is not driven
// Warning: Net 'uc_31' in module 'cpu' is not driven
// Warning: Net 'uc_32' in module 'cpu' is not driven
// Warning: Net 'uc_33' in module 'cpu' is not driven
// Warning: Net 'uc_34' in module 'cpu' is not driven
// Warning: Net 'uc_35' in module 'cpu' is not driven
// Warning: Net 'uc_36' in module 'cpu' is not driven
// Warning: Net 'uc_37' in module 'cpu' is not driven
// Warning: Net 'uc_38' in module 'cpu' is not driven
// Warning: Net 'uc_39' in module 'cpu' is not driven
// Warning: Floating input 'chip_en' at instance 'RAM' in module 'main_mem'
// Warning: Net 'mem_sel[1]' in module 'MemGen_32_11' has no pins
// Warning: Net 'DAddr[31]' in module 'decoder' is not driven
// Warning: Net 'DAddr[30]' in module 'decoder' is not driven
// Warning: Net 'DAddr[29]' in module 'decoder' is not driven
// Warning: Net 'DAddr[28]' in module 'decoder' is not driven
// Warning: Net 'DAddr[27]' in module 'decoder' is not driven
// Warning: Net 'DAddr[26]' in module 'decoder' is not driven
// Warning: Net 'DAddr[25]' in module 'decoder' is not driven
// Warning: Net 'DAddr[24]' in module 'decoder' is not driven
// Warning: Net 'DAddr[23]' in module 'decoder' is not driven
// Warning: Net 'DAddr[22]' in module 'decoder' is not driven
// Warning: Net 'DAddr[21]' in module 'decoder' is not driven
// Warning: Net 'DAddr[20]' in module 'decoder' is not driven
// Warning: Net 'DAddr[19]' in module 'decoder' is not driven
// Warning: Net 'DAddr[18]' in module 'decoder' is not driven
// Warning: Net 'DAddr[17]' in module 'decoder' is not driven
// Warning: Net 'DAddr[16]' in module 'decoder' is not driven
// Warning: Net 'DAddr[15]' in module 'decoder' is not driven
// Warning: Net 'DAddr[14]' in module 'decoder' is not driven
// Warning: Net 'DAddr[13]' in module 'decoder' is not driven
// Warning: Net 'WData[31]' in module 'decoder' is not driven
// Warning: Net 'WData[30]' in module 'decoder' is not driven
// Warning: Net 'WData[29]' in module 'decoder' is not driven
// Warning: Net 'WData[28]' in module 'decoder' is not driven
// Warning: Net 'WData[27]' in module 'decoder' is not driven
// Warning: Net 'WData[26]' in module 'decoder' is not driven
// Warning: Net 'WData[25]' in module 'decoder' is not driven
// Warning: Net 'WData[24]' in module 'decoder' is not driven
// Warning: Net 'WData[23]' in module 'decoder' is not driven
// Warning: Net 'WData[22]' in module 'decoder' is not driven
// Warning: Net 'WData[21]' in module 'decoder' is not driven
// Warning: Net 'WData[20]' in module 'decoder' is not driven
// Warning: Net 'WData[19]' in module 'decoder' is not driven
// Warning: Net 'WData[18]' in module 'decoder' is not driven
// Warning: Net 'WData[17]' in module 'decoder' is not driven
// Warning: Net 'WData[16]' in module 'decoder' is not driven
// Warning: Net 'WData[15]' in module 'decoder' is not driven
// Warning: Net 'WData[14]' in module 'decoder' is not driven
// Warning: Net 'WData[13]' in module 'decoder' is not driven
// Warning: Net 'WData[12]' in module 'decoder' is not driven
// Warning: Net 'WData[11]' in module 'decoder' is not driven
// Warning: Net 'WData[10]' in module 'decoder' is not driven
// Warning: Net 'WData[9]' in module 'decoder' is not driven
// Warning: Net 'WData[8]' in module 'decoder' is not driven
// Warning: Net 'WData[7]' in module 'decoder' is not driven
// Warning: Net 'WData[6]' in module 'decoder' is not driven
// Warning: Net 'WData[5]' in module 'decoder' is not driven
// Warning: Net 'WData[4]' in module 'decoder' is not driven
// Warning: Net 'WData[3]' in module 'decoder' is not driven
// Warning: Net 'WData[2]' in module 'decoder' is not driven
// Warning: Net 'WData[1]' in module 'decoder' is not driven
// Warning: Net 'WData[0]' in module 'decoder' is not driven
// Warning: Net 'Rs1[4]' in module 'decoder' is not driven
// Warning: Net 'Rs1[3]' in module 'decoder' is not driven
// Warning: Net 'Rs1[2]' in module 'decoder' is not driven
// Warning: Net 'Rs1[1]' in module 'decoder' is not driven
// Warning: Net 'Rs1[0]' in module 'decoder' is not driven
// Warning: Net 'Rs2[4]' in module 'decoder' is not driven
// Warning: Net 'Rs2[3]' in module 'decoder' is not driven
// Warning: Net 'Rs2[2]' in module 'decoder' is not driven
// Warning: Net 'Rs2[1]' in module 'decoder' is not driven
// Warning: Net 'Rs2[0]' in module 'decoder' is not driven
// Warning: Net 'Rd[4]' in module 'decoder' is not driven
// Warning: Net 'Rd[3]' in module 'decoder' is not driven
// Warning: Net 'Rd[2]' in module 'decoder' is not driven
// Warning: Net 'Rd[1]' in module 'decoder' is not driven
// Warning: Net 'Rd[0]' in module 'decoder' is not driven
// sub-command: set_design_level physical_block
// sub-command: set_shift_register_identification off
// sub-command: add_nonscan_instances -instances "{/theMem/\IRData_reg[31] } {/theMem/\IRData_reg[30] } {/theMem/\IRData_reg[29] } {/theMem/\IRData_reg[28] } {/theMem/\IRData_reg[27] } {/theMem/\IRData_reg[26] } {/theMem/\IRData_reg[25] } {/theMem/\IRData_reg[24] } {/theMem/\IRData_reg[23] } {/theMem/\IRData_reg[22] } {/theMem/\IRData_reg[21] } {/theMem/\IRData_reg[20] } {/theMem/\IRData_reg[19] } {/theMem/\IRData_reg[18] } {/theMem/\IRData_reg[17] } {/theMem/\IRData_reg[16] } {/theMem/\IRData_reg[15] } {/theMem/\IRData_reg[14] } {/theMem/\IRData_reg[13] } {/theMem/\IRData_reg[12] } {/theMem/\IRData_reg[11] } {/theMem/\IRData_reg[10] } {/theMem/\IRData_reg[9] } {/theMem/\IRData_reg[8] } {/theMem/\IRData_reg[7] } {/theMem/\IRData_reg[6] } {/theMem/\IRData_reg[5] } {/theMem/\IRData_reg[4] } {/theMem/\IRData_reg[3] } {/theMem/\IRData_reg[2] } {/theMem/\IRData_reg[1] } {/theMem/\IRData_reg[0] } {/theMem/\mem_addr_reg[10] } {/theMem/\mem_addr_reg[9] } {/theMem/\mem_addr_reg[8] } {/theMem/\mem_addr_reg[7] } {/theMem/\mem_addr_reg[6] } {/theMem/\mem_addr_reg[5] } {/theMem/\mem_addr_reg[4] } {/theMem/\mem_addr_reg[3] } {/theMem/\mem_addr_reg[2] } {/theMem/\mem_addr_reg[1] } {/theMem/\mem_addr_reg[0] } {/theMem/\drTmp_reg[31] } {/theMem/\drTmp_reg[30] } {/theMem/\drTmp_reg[29] } {/theMem/\drTmp_reg[28] } {/theMem/\drTmp_reg[27] } {/theMem/\drTmp_reg[26] } {/theMem/\drTmp_reg[25] } {/theMem/\drTmp_reg[24] } {/theMem/\drTmp_reg[23] } {/theMem/\drTmp_reg[22] } {/theMem/\drTmp_reg[21] } {/theMem/\drTmp_reg[20] } {/theMem/\drTmp_reg[19] } {/theMem/\drTmp_reg[18] } {/theMem/\drTmp_reg[17] } {/theMem/\drTmp_reg[16] } {/theMem/\drTmp_reg[15] } {/theMem/\drTmp_reg[14] } {/theMem/\drTmp_reg[13] } {/theMem/\drTmp_reg[12] } {/theMem/\drTmp_reg[11] } {/theMem/\drTmp_reg[10] } {/theMem/\drTmp_reg[9] } {/theMem/\drTmp_reg[8] } {/theMem/\drTmp_reg[7] } {/theMem/\drTmp_reg[6] } {/theMem/\drTmp_reg[5] } {/theMem/\drTmp_reg[4] } {/theMem/\drTmp_reg[3] } {/theMem/\drTmp_reg[2] } {/theMem/\drTmp_reg[1] } {/theMem/\drTmp_reg[0] } {/theMem/\mem_wdata_reg[31] } {/theMem/\mem_wdata_reg[30] } {/theMem/\mem_wdata_reg[29] } {/theMem/\mem_wdata_reg[28] } {/theMem/\mem_wdata_reg[27] } {/theMem/\mem_wdata_reg[26] } {/theMem/\mem_wdata_reg[25] } {/theMem/\mem_wdata_reg[24] } {/theMem/\mem_wdata_reg[23] } {/theMem/\mem_wdata_reg[22] } {/theMem/\mem_wdata_reg[21] } {/theMem/\mem_wdata_reg[20] } {/theMem/\mem_wdata_reg[19] } {/theMem/\mem_wdata_reg[18] } {/theMem/\mem_wdata_reg[17] } {/theMem/\mem_wdata_reg[16] } {/theMem/\mem_wdata_reg[15] } {/theMem/\mem_wdata_reg[14] } {/theMem/\mem_wdata_reg[13] } {/theMem/\mem_wdata_reg[12] } {/theMem/\mem_wdata_reg[11] } {/theMem/\mem_wdata_reg[10] } {/theMem/\mem_wdata_reg[9] } {/theMem/\mem_wdata_reg[8] } {/theMem/\mem_wdata_reg[7] } {/theMem/\mem_wdata_reg[6] } {/theMem/\mem_wdata_reg[5] } {/theMem/\mem_wdata_reg[4] } {/theMem/\mem_wdata_reg[3] } {/theMem/\mem_wdata_reg[2] } {/theMem/\mem_wdata_reg[1] } {/theMem/\mem_wdata_reg[0] } "
// sub-command: add_clocks 0 " clk_25mhz "
// sub-command: set_scan_enable scan_en -active high
// sub-command: add_input_constraints btn[0] -C1
// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_1
// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_2
// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_3
// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_4
// sub-command: add_black_boxes -modules " MemGen_16_10 "
// sub-command: set_scan_insertion_options -single_clock_edge_chains on -si_port_format oas_ts_si[%d] -so_port_format oas_ts_so[%d]
// sub-command: set_system_mode analysis
// Warning: Rule FN1 violation occurs 157 times
// Warning: Rule FP13 violation occurs 1 times
// Flattening process completed, cell instances=4379, gates=18234, PIs=13, POs=12, CPU time=0.09 sec.
// ---------------------------------------------------------------------------
// Begin circuit learning analyses.
// --------------------------------
// Learning completed, CPU time=0.01 sec.
// ---------------------------------------------------------------------------
// Begin scan chain identification process, memory elements = 1194,
// sequential library cells = 1194.
// ---------------------------------------------------------------------------
// Warning: Model 'DLH_X1_LVT' has no muxscan scan equivalent and is treated as nonscan model
// ------------------------------------------------------------------------------
// 170 sequential library cells are treated as non-scan.
// ------------------------------------------------------------------------------
// 63 sequential library cells missing mux-scan equivalent.
// 107 sequential library cells defined non-scan.
// ---------------------------------------------------------------------------
// Begin scannability rules checking for 1024 sequential library cells.
// ---------------------------------------------------------------------------
// 1024 sequential library cells identified as scannable.
// ---------------------------------------------------------------------------
// Begin transparent latch checking for 63 latches.
// ---------------------------------------------------------------------------
// Warning: 32 latches not transparent due to uncontrollable. (D6)
// Number transparent latches = 31.
// ---------------------------------------------------------------------------
// Begin scan clock rules checking.
// ---------------------------------------------------------------------------
// 1 scan clock/set/reset lines have been identified.
// All scan clocks successfully passed off-state check.
// 1131 sequential cells passed clock stability checking.
// There were 43 clock rule C3 fails (clock may capture data affected by its captured data).
// Note: Trailing edge triggered device can capture data affected by leading edge.
// ---------------------------------------------------------------------------
// 170 non-scan memory elements are identified.
// ---------------------------------------------------------------------------
// 32 non-scan memory elements are identified as TIE-X. (D5)
// 107 non-scan memory elements are identified as INIT-X. (D5)
// 31 non-scan memory elements are identified as TLA. (D5)
// ---------------------------------------------------------------------------
// Number of targeted sequential library cells = 1024
// Warning: The tool may require a shift-capture clock during insertion,
// but no 'shift_capture_clock' DFT signal was identified
// and no TCLK source was specified using the command 'set_scan_signals -tclk'.
// Note: The system clock 'clk_25mhz' will be used as the shift-capture clock, if needed.
// sub-command: report_drc_rules
C3: #fails=43 handling=note (clock may capture data affected by its captured data)
D5: #fails=170 handling=warning (non-scan memory element)
D6: #fails=32 handling=warning (non-transparent non-scan latches)
// sub-command: create_scan_chain_family scanChain_1 -include_elements "{/\thePC_CurrentPC_reg[0] } {/\thePC_CurrentPC_reg[10] } {/\thePC_CurrentPC_reg[11] } {/\thePC_CurrentPC_reg[12] } {/\thePC_CurrentPC_reg[13] } {/\thePC_CurrentPC_reg[14] } {/\thePC_CurrentPC_reg[15] } {/\thePC_CurrentPC_reg[16] } {/\thePC_CurrentPC_reg[17] } {/\thePC_CurrentPC_reg[18] } {/\thePC_CurrentPC_reg[19] } {/\thePC_CurrentPC_reg[1] } {/\thePC_CurrentPC_reg[20] } {/\thePC_CurrentPC_reg[21] } {/\thePC_CurrentPC_reg[22] } {/\thePC_CurrentPC_reg[23] } {/\thePC_CurrentPC_reg[24] } {/\thePC_CurrentPC_reg[25] } {/\thePC_CurrentPC_reg[26] } {/\thePC_CurrentPC_reg[27] } {/\thePC_CurrentPC_reg[28] } {/\thePC_CurrentPC_reg[29] } {/\thePC_CurrentPC_reg[2] } {/\thePC_CurrentPC_reg[30] } {/\thePC_CurrentPC_reg[31] } {/\thePC_CurrentPC_reg[3] } {/\thePC_CurrentPC_reg[4] } {/\thePC_CurrentPC_reg[5] } {/\thePC_CurrentPC_reg[6] } {/\thePC_CurrentPC_reg[7] } {/\thePC_CurrentPC_reg[8] } {/\thePC_CurrentPC_reg[9] } {/theRegisters/\registers_reg[10][0] } {/theRegisters/\registers_reg[10][10] } {/theRegisters/\registers_reg[10][11] } {/theRegisters/\registers_reg[10][12] } {/theRegisters/\registers_reg[10][13] } {/theRegisters/\registers_reg[10][14] } {/theRegisters/\registers_reg[10][15] } {/theRegisters/\registers_reg[10][16] } {/theRegisters/\registers_reg[10][17] } {/theRegisters/\registers_reg[10][18] } {/theRegisters/\registers_reg[10][19] } {/theRegisters/\registers_reg[10][1] } {/theRegisters/\registers_reg[10][20] } {/theRegisters/\registers_reg[10][21] } {/theRegisters/\registers_reg[10][22] } {/theRegisters/\registers_reg[10][23] } {/theRegisters/\registers_reg[10][24] } {/theRegisters/\registers_reg[10][25] } {/theRegisters/\registers_reg[10][26] } {/theRegisters/\registers_reg[10][27] } {/theRegisters/\registers_reg[10][28] } {/theRegisters/\registers_reg[10][29] } {/theRegisters/\registers_reg[10][2] } {/theRegisters/\registers_reg[10][30] } {/theRegisters/\registers_reg[10][31] } {/theRegisters/\registers_reg[10][3] } {/theRegisters/\registers_reg[10][4] } {/theRegisters/\registers_reg[10][5] } {/theRegisters/\registers_reg[10][6] } {/theRegisters/\registers_reg[10][7] } {/theRegisters/\registers_reg[10][8] } {/theRegisters/\registers_reg[10][9] } {/theRegisters/\registers_reg[11][0] } {/theRegisters/\registers_reg[11][10] } {/theRegisters/\registers_reg[11][11] } {/theRegisters/\registers_reg[11][12] } {/theRegisters/\registers_reg[11][13] } {/theRegisters/\registers_reg[11][14] } {/theRegisters/\registers_reg[11][15] } {/theRegisters/\registers_reg[11][16] } {/theRegisters/\registers_reg[11][17] } {/theRegisters/\registers_reg[11][18] } {/theRegisters/\registers_reg[11][19] } {/theRegisters/\registers_reg[11][1] } {/theRegisters/\registers_reg[11][20] } {/theRegisters/\registers_reg[11][21] } {/theRegisters/\registers_reg[11][22] } {/theRegisters/\registers_reg[11][23] } {/theRegisters/\registers_reg[11][24] } {/theRegisters/\registers_reg[11][25] } {/theRegisters/\registers_reg[11][26] } {/theRegisters/\registers_reg[11][27] } {/theRegisters/\registers_reg[11][28] } {/theRegisters/\registers_reg[11][29] } {/theRegisters/\registers_reg[11][2] } {/theRegisters/\registers_reg[11][30] } {/theRegisters/\registers_reg[11][31] } {/theRegisters/\registers_reg[11][3] } {/theRegisters/\registers_reg[11][4] } {/theRegisters/\registers_reg[11][5] } {/theRegisters/\registers_reg[11][6] } {/theRegisters/\registers_reg[11][7] } {/theRegisters/\registers_reg[11][8] } {/theRegisters/\registers_reg[11][9] } {/theRegisters/\registers_reg[12][0] } {/theRegisters/\registers_reg[12][10] } {/theRegisters/\registers_reg[12][11] } {/theRegisters/\registers_reg[12][12] } {/theRegisters/\registers_reg[12][13] } {/theRegisters/\registers_reg[12][14] } {/theRegisters/\registers_reg[12][15] } {/theRegisters/\registers_reg[12][16] } {/theRegisters/\registers_reg[12][17] } {/theRegisters/\registers_reg[12][18] } {/theRegisters/\registers_reg[12][19] } {/theRegisters/\registers_reg[12][1] } {/theRegisters/\registers_reg[12][20] } {/theRegisters/\registers_reg[12][21] } {/theRegisters/\registers_reg[12][22] } {/theRegisters/\registers_reg[12][23] } {/theRegisters/\registers_reg[12][24] } {/theRegisters/\registers_reg[12][25] } {/theRegisters/\registers_reg[12][26] } {/theRegisters/\registers_reg[12][27] } {/theRegisters/\registers_reg[12][28] } {/theRegisters/\registers_reg[12][29] } {/theRegisters/\registers_reg[12][2] } {/theRegisters/\registers_reg[12][30] } {/theRegisters/\registers_reg[12][31] } {/theRegisters/\registers_reg[12][3] } {/theRegisters/\registers_reg[12][4] } {/theRegisters/\registers_reg[12][5] } {/theRegisters/\registers_reg[12][6] } {/theRegisters/\registers_reg[12][7] } {/theRegisters/\registers_reg[12][8] } {/theRegisters/\registers_reg[12][9] } {/theRegisters/\registers_reg[13][0] } {/theRegisters/\registers_reg[13][10] } {/theRegisters/\registers_reg[13][11] } {/theRegisters/\registers_reg[13][12] } {/theRegisters/\registers_reg[13][13] } {/theRegisters/\registers_reg[13][14] } {/theRegisters/\registers_reg[13][15] } {/theRegisters/\registers_reg[13][16] } {/theRegisters/\registers_reg[13][17] } {/theRegisters/\registers_reg[13][18] } {/theRegisters/\registers_reg[13][19] } {/theRegisters/\registers_reg[13][1] } {/theRegisters/\registers_reg[13][20] } {/theRegisters/\registers_reg[13][21] } {/theRegisters/\registers_reg[13][22] } {/theRegisters/\registers_reg[13][23] } {/theRegisters/\registers_reg[13][24] } {/theRegisters/\registers_reg[13][25] } {/theRegisters/\registers_reg[13][26] } {/theRegisters/\registers_reg[13][27] } {/theRegisters/\registers_reg[13][28] } {/theRegisters/\registers_reg[13][29] } {/theRegisters/\registers_reg[13][2] } {/theRegisters/\registers_reg[13][30] } {/theRegisters/\registers_reg[13][31] } {/theRegisters/\registers_reg[13][3] } {/theRegisters/\registers_reg[13][4] } {/theRegisters/\registers_reg[13][5] } {/theRegisters/\registers_reg[13][6] } {/theRegisters/\registers_reg[13][7] } {/theRegisters/\registers_reg[13][8] } {/theRegisters/\registers_reg[13][9] } {/theRegisters/\registers_reg[14][0] } {/theRegisters/\registers_reg[14][10] } {/theRegisters/\registers_reg[14][11] } {/theRegisters/\registers_reg[14][12] } {/theRegisters/\registers_reg[14][13] } {/theRegisters/\registers_reg[14][14] } {/theRegisters/\registers_reg[14][15] } {/theRegisters/\registers_reg[14][16] } {/theRegisters/\registers_reg[14][17] } {/theRegisters/\registers_reg[14][18] } {/theRegisters/\registers_reg[14][19] } {/theRegisters/\registers_reg[14][1] } {/theRegisters/\registers_reg[14][20] } {/theRegisters/\registers_reg[14][21] } {/theRegisters/\registers_reg[14][22] } {/theRegisters/\registers_reg[14][23] } {/theRegisters/\registers_reg[14][24] } {/theRegisters/\registers_reg[14][25] } {/theRegisters/\registers_reg[14][26] } {/theRegisters/\registers_reg[14][27] } {/theRegisters/\registers_reg[14][28] } {/theRegisters/\registers_reg[14][29] } {/theRegisters/\registers_reg[14][2] } {/theRegisters/\registers_reg[14][30] } {/theRegisters/\registers_reg[14][31] } {/theRegisters/\registers_reg[14][3] } {/theRegisters/\registers_reg[14][4] } {/theRegisters/\registers_reg[14][5] } {/theRegisters/\registers_reg[14][6] } {/theRegisters/\registers_reg[14][7] } {/theRegisters/\registers_reg[14][8] } {/theRegisters/\registers_reg[14][9] } {/theRegisters/\registers_reg[15][0] } {/theRegisters/\registers_reg[15][10] } {/theRegisters/\registers_reg[15][11] } {/theRegisters/\registers_reg[15][12] } {/theRegisters/\registers_reg[15][13] } {/theRegisters/\registers_reg[15][14] } {/theRegisters/\registers_reg[15][15] } {/theRegisters/\registers_reg[15][16] } {/theRegisters/\registers_reg[15][17] } {/theRegisters/\registers_reg[15][18] } {/theRegisters/\registers_reg[15][19] } {/theRegisters/\registers_reg[15][1] } {/theRegisters/\registers_reg[15][20] } {/theRegisters/\registers_reg[15][21] } {/theRegisters/\registers_reg[15][22] } {/theRegisters/\registers_reg[15][23] } {/theRegisters/\registers_reg[15][24] } {/theRegisters/\registers_reg[15][25] } {/theRegisters/\registers_reg[15][26] } {/theRegisters/\registers_reg[15][27] } {/theRegisters/\registers_reg[15][28] } {/theRegisters/\registers_reg[15][29] } {/theRegisters/\registers_reg[15][2] } {/theRegisters/\registers_reg[15][30] } {/theRegisters/\registers_reg[15][31] } {/theRegisters/\registers_reg[15][3] } {/theRegisters/\registers_reg[15][4] } {/theRegisters/\registers_reg[15][5] } {/theRegisters/\registers_reg[15][6] } {/theRegisters/\registers_reg[15][7] } {/theRegisters/\registers_reg[15][8] } {/theRegisters/\registers_reg[15][9] } {/theRegisters/\registers_reg[16][0] } {/theRegisters/\registers_reg[16][10] } {/theRegisters/\registers_reg[16][11] } {/theRegisters/\registers_reg[16][12] } {/theRegisters/\registers_reg[16][13] } {/theRegisters/\registers_reg[16][14] } {/theRegisters/\registers_reg[16][15] } {/theRegisters/\registers_reg[16][16] } {/theRegisters/\registers_reg[16][17] } {/theRegisters/\registers_reg[16][18] } {/theRegisters/\registers_reg[16][19] } {/theRegisters/\registers_reg[16][1] } {/theRegisters/\registers_reg[16][20] } {/theRegisters/\registers_reg[16][21] } {/theRegisters/\registers_reg[16][22] } {/theRegisters/\registers_reg[16][23] } {/theRegisters/\registers_reg[16][24] } {/theRegisters/\registers_reg[16][25] } {/theRegisters/\registers_reg[16][26] } {/theRegisters/\registers_reg[16][27] } {/theRegisters/\registers_reg[16][28] } {/theRegisters/\registers_reg[16][29] } {/theRegisters/\registers_reg[16][2] } {/theRegisters/\registers_reg[16][30] } {/theRegisters/\registers_reg[16][31] } {/theRegisters/\registers_reg[16][3] } {/theRegisters/\registers_reg[16][4] } {/theRegisters/\registers_reg[16][5] } {/theRegisters/\registers_reg[16][6] } {/theRegisters/\registers_reg[16][7] } {/theRegisters/\registers_reg[16][8] } {/theRegisters/\registers_reg[16][9] } " -si_connections "SI_1 " -so_connections "SO_1 " -chain_count 1
// sub-command: create_scan_chain_family scanChain_2 -include_elements "{/theRegisters/\registers_reg[17][0] } {/theRegisters/\registers_reg[17][10] } {/theRegisters/\registers_reg[17][11] } {/theRegisters/\registers_reg[17][12] } {/theRegisters/\registers_reg[17][13] } {/theRegisters/\registers_reg[17][14] } {/theRegisters/\registers_reg[17][15] } {/theRegisters/\registers_reg[17][16] } {/theRegisters/\registers_reg[17][17] } {/theRegisters/\registers_reg[17][18] } {/theRegisters/\registers_reg[17][19] } {/theRegisters/\registers_reg[17][1] } {/theRegisters/\registers_reg[17][20] } {/theRegisters/\registers_reg[17][21] } {/theRegisters/\registers_reg[17][22] } {/theRegisters/\registers_reg[17][23] } {/theRegisters/\registers_reg[17][24] } {/theRegisters/\registers_reg[17][25] } {/theRegisters/\registers_reg[17][26] } {/theRegisters/\registers_reg[17][27] } {/theRegisters/\registers_reg[17][28] } {/theRegisters/\registers_reg[17][29] } {/theRegisters/\registers_reg[17][2] } {/theRegisters/\registers_reg[17][30] } {/theRegisters/\registers_reg[17][31] } {/theRegisters/\registers_reg[17][3] } {/theRegisters/\registers_reg[17][4] } {/theRegisters/\registers_reg[17][5] } {/theRegisters/\registers_reg[17][6] } {/theRegisters/\registers_reg[17][7] } {/theRegisters/\registers_reg[17][8] } {/theRegisters/\registers_reg[17][9] } {/theRegisters/\registers_reg[18][0] } {/theRegisters/\registers_reg[18][10] } {/theRegisters/\registers_reg[18][11] } {/theRegisters/\registers_reg[18][12] } {/theRegisters/\registers_reg[18][13] } {/theRegisters/\registers_reg[18][14] } {/theRegisters/\registers_reg[18][15] } {/theRegisters/\registers_reg[18][16] } {/theRegisters/\registers_reg[18][17] } {/theRegisters/\registers_reg[18][18] } {/theRegisters/\registers_reg[18][19] } {/theRegisters/\registers_reg[18][1] } {/theRegisters/\registers_reg[18][20] } {/theRegisters/\registers_reg[18][21] } {/theRegisters/\registers_reg[18][22] } {/theRegisters/\registers_reg[18][23] } {/theRegisters/\registers_reg[18][24] } {/theRegisters/\registers_reg[18][25] } {/theRegisters/\registers_reg[18][26] } {/theRegisters/\registers_reg[18][27] } {/theRegisters/\registers_reg[18][28] } {/theRegisters/\registers_reg[18][29] } {/theRegisters/\registers_reg[18][2] } {/theRegisters/\registers_reg[18][30] } {/theRegisters/\registers_reg[18][31] } {/theRegisters/\registers_reg[18][3] } {/theRegisters/\registers_reg[18][4] } {/theRegisters/\registers_reg[18][5] } {/theRegisters/\registers_reg[18][6] } {/theRegisters/\registers_reg[18][7] } {/theRegisters/\registers_reg[18][8] } {/theRegisters/\registers_reg[18][9] } {/theRegisters/\registers_reg[19][0] } {/theRegisters/\registers_reg[19][10] } {/theRegisters/\registers_reg[19][11] } {/theRegisters/\registers_reg[19][12] } {/theRegisters/\registers_reg[19][13] } {/theRegisters/\registers_reg[19][14] } {/theRegisters/\registers_reg[19][15] } {/theRegisters/\registers_reg[19][16] } {/theRegisters/\registers_reg[19][17] } {/theRegisters/\registers_reg[19][18] } {/theRegisters/\registers_reg[19][19] } {/theRegisters/\registers_reg[19][1] } {/theRegisters/\registers_reg[19][20] } {/theRegisters/\registers_reg[19][21] } {/theRegisters/\registers_reg[19][22] } {/theRegisters/\registers_reg[19][23] } {/theRegisters/\registers_reg[19][24] } {/theRegisters/\registers_reg[19][25] } {/theRegisters/\registers_reg[19][26] } {/theRegisters/\registers_reg[19][27] } {/theRegisters/\registers_reg[19][28] } {/theRegisters/\registers_reg[19][29] } {/theRegisters/\registers_reg[19][2] } {/theRegisters/\registers_reg[19][30] } {/theRegisters/\registers_reg[19][31] } {/theRegisters/\registers_reg[19][3] } {/theRegisters/\registers_reg[19][4] } {/theRegisters/\registers_reg[19][5] } {/theRegisters/\registers_reg[19][6] } {/theRegisters/\registers_reg[19][7] } {/theRegisters/\registers_reg[19][8] } {/theRegisters/\registers_reg[19][9] } {/theRegisters/\registers_reg[1][0] } {/theRegisters/\registers_reg[1][10] } {/theRegisters/\registers_reg[1][11] } {/theRegisters/\registers_reg[1][12] } {/theRegisters/\registers_reg[1][13] } {/theRegisters/\registers_reg[1][14] } {/theRegisters/\registers_reg[1][15] } {/theRegisters/\registers_reg[1][16] } {/theRegisters/\registers_reg[1][17] } {/theRegisters/\registers_reg[1][18] } {/theRegisters/\registers_reg[1][19] } {/theRegisters/\registers_reg[1][1] } {/theRegisters/\registers_reg[1][20] } {/theRegisters/\registers_reg[1][21] } {/theRegisters/\registers_reg[1][22] } {/theRegisters/\registers_reg[1][23] } {/theRegisters/\registers_reg[1][24] } {/theRegisters/\registers_reg[1][25] } {/theRegisters/\registers_reg[1][26] } {/theRegisters/\registers_reg[1][27] } {/theRegisters/\registers_reg[1][28] } {/theRegisters/\registers_reg[1][29] } {/theRegisters/\registers_reg[1][2] } {/theRegisters/\registers_reg[1][30] } {/theRegisters/\registers_reg[1][31] } {/theRegisters/\registers_reg[1][3] } {/theRegisters/\registers_reg[1][4] } {/theRegisters/\registers_reg[1][5] } {/theRegisters/\registers_reg[1][6] } {/theRegisters/\registers_reg[1][7] } {/theRegisters/\registers_reg[1][8] } {/theRegisters/\registers_reg[1][9] } {/theRegisters/\registers_reg[20][0] } {/theRegisters/\registers_reg[20][10] } {/theRegisters/\registers_reg[20][11] } {/theRegisters/\registers_reg[20][12] } {/theRegisters/\registers_reg[20][13] } {/theRegisters/\registers_reg[20][14] } {/theRegisters/\registers_reg[20][15] } {/theRegisters/\registers_reg[20][16] } {/theRegisters/\registers_reg[20][17] } {/theRegisters/\registers_reg[20][18] } {/theRegisters/\registers_reg[20][19] } {/theRegisters/\registers_reg[20][1] } {/theRegisters/\registers_reg[20][20] } {/theRegisters/\registers_reg[20][21] } {/theRegisters/\registers_reg[20][22] } {/theRegisters/\registers_reg[20][23] } {/theRegisters/\registers_reg[20][24] } {/theRegisters/\registers_reg[20][25] } {/theRegisters/\registers_reg[20][26] } {/theRegisters/\registers_reg[20][27] } {/theRegisters/\registers_reg[20][28] } {/theRegisters/\registers_reg[20][29] } {/theRegisters/\registers_reg[20][2] } {/theRegisters/\registers_reg[20][30] } {/theRegisters/\registers_reg[20][31] } {/theRegisters/\registers_reg[20][3] } {/theRegisters/\registers_reg[20][4] } {/theRegisters/\registers_reg[20][5] } {/theRegisters/\registers_reg[20][6] } {/theRegisters/\registers_reg[20][7] } {/theRegisters/\registers_reg[20][8] } {/theRegisters/\registers_reg[20][9] } {/theRegisters/\registers_reg[21][0] } {/theRegisters/\registers_reg[21][10] } {/theRegisters/\registers_reg[21][11] } {/theRegisters/\registers_reg[21][12] } {/theRegisters/\registers_reg[21][13] } {/theRegisters/\registers_reg[21][14] } {/theRegisters/\registers_reg[21][15] } {/theRegisters/\registers_reg[21][16] } {/theRegisters/\registers_reg[21][17] } {/theRegisters/\registers_reg[21][18] } {/theRegisters/\registers_reg[21][19] } {/theRegisters/\registers_reg[21][1] } {/theRegisters/\registers_reg[21][20] } {/theRegisters/\registers_reg[21][21] } {/theRegisters/\registers_reg[21][22] } {/theRegisters/\registers_reg[21][23] } {/theRegisters/\registers_reg[21][24] } {/theRegisters/\registers_reg[21][25] } {/theRegisters/\registers_reg[21][26] } {/theRegisters/\registers_reg[21][27] } {/theRegisters/\registers_reg[21][28] } {/theRegisters/\registers_reg[21][29] } {/theRegisters/\registers_reg[21][2] } {/theRegisters/\registers_reg[21][30] } {/theRegisters/\registers_reg[21][31] } {/theRegisters/\registers_reg[21][3] } {/theRegisters/\registers_reg[21][4] } {/theRegisters/\registers_reg[21][5] } {/theRegisters/\registers_reg[21][6] } {/theRegisters/\registers_reg[21][7] } {/theRegisters/\registers_reg[21][8] } {/theRegisters/\registers_reg[21][9] } {/theRegisters/\registers_reg[22][0] } {/theRegisters/\registers_reg[22][10] } {/theRegisters/\registers_reg[22][11] } {/theRegisters/\registers_reg[22][12] } {/theRegisters/\registers_reg[22][13] } {/theRegisters/\registers_reg[22][14] } {/theRegisters/\registers_reg[22][15] } {/theRegisters/\registers_reg[22][16] } {/theRegisters/\registers_reg[22][17] } {/theRegisters/\registers_reg[22][18] } {/theRegisters/\registers_reg[22][19] } {/theRegisters/\registers_reg[22][1] } {/theRegisters/\registers_reg[22][20] } {/theRegisters/\registers_reg[22][21] } {/theRegisters/\registers_reg[22][22] } {/theRegisters/\registers_reg[22][23] } {/theRegisters/\registers_reg[22][24] } {/theRegisters/\registers_reg[22][25] } {/theRegisters/\registers_reg[22][26] } {/theRegisters/\registers_reg[22][27] } {/theRegisters/\registers_reg[22][28] } {/theRegisters/\registers_reg[22][29] } {/theRegisters/\registers_reg[22][2] } {/theRegisters/\registers_reg[22][30] } {/theRegisters/\registers_reg[22][31] } {/theRegisters/\registers_reg[22][3] } {/theRegisters/\registers_reg[22][4] } {/theRegisters/\registers_reg[22][5] } {/theRegisters/\registers_reg[22][6] } {/theRegisters/\registers_reg[22][7] } {/theRegisters/\registers_reg[22][8] } {/theRegisters/\registers_reg[22][9] } {/theRegisters/\registers_reg[23][0] } {/theRegisters/\registers_reg[23][10] } {/theRegisters/\registers_reg[23][11] } {/theRegisters/\registers_reg[23][12] } {/theRegisters/\registers_reg[23][13] } {/theRegisters/\registers_reg[23][14] } {/theRegisters/\registers_reg[23][15] } {/theRegisters/\registers_reg[23][16] } {/theRegisters/\registers_reg[23][17] } {/theRegisters/\registers_reg[23][18] } {/theRegisters/\registers_reg[23][19] } {/theRegisters/\registers_reg[23][1] } {/theRegisters/\registers_reg[23][20] } {/theRegisters/\registers_reg[23][21] } {/theRegisters/\registers_reg[23][22] } {/theRegisters/\registers_reg[23][23] } {/theRegisters/\registers_reg[23][24] } {/theRegisters/\registers_reg[23][25] } {/theRegisters/\registers_reg[23][26] } {/theRegisters/\registers_reg[23][27] } {/theRegisters/\registers_reg[23][28] } {/theRegisters/\registers_reg[23][29] } {/theRegisters/\registers_reg[23][2] } {/theRegisters/\registers_reg[23][30] } {/theRegisters/\registers_reg[23][31] } {/theRegisters/\registers_reg[23][3] } {/theRegisters/\registers_reg[23][4] } {/theRegisters/\registers_reg[23][5] } {/theRegisters/\registers_reg[23][6] } {/theRegisters/\registers_reg[23][7] } {/theRegisters/\registers_reg[23][8] } {/theRegisters/\registers_reg[23][9] } " -si_connections "SI_2 " -so_connections "SO_2 " -chain_count 1
// sub-command: create_scan_chain_family scanChain_3 -include_elements "{/theRegisters/\registers_reg[24][0] } {/theRegisters/\registers_reg[24][10] } {/theRegisters/\registers_reg[24][11] } {/theRegisters/\registers_reg[24][12] } {/theRegisters/\registers_reg[24][13] } {/theRegisters/\registers_reg[24][14] } {/theRegisters/\registers_reg[24][15] } {/theRegisters/\registers_reg[24][16] } {/theRegisters/\registers_reg[24][17] } {/theRegisters/\registers_reg[24][18] } {/theRegisters/\registers_reg[24][19] } {/theRegisters/\registers_reg[24][1] } {/theRegisters/\registers_reg[24][20] } {/theRegisters/\registers_reg[24][21] } {/theRegisters/\registers_reg[24][22] } {/theRegisters/\registers_reg[24][23] } {/theRegisters/\registers_reg[24][24] } {/theRegisters/\registers_reg[24][25] } {/theRegisters/\registers_reg[24][26] } {/theRegisters/\registers_reg[24][27] } {/theRegisters/\registers_reg[24][28] } {/theRegisters/\registers_reg[24][29] } {/theRegisters/\registers_reg[24][2] } {/theRegisters/\registers_reg[24][30] } {/theRegisters/\registers_reg[24][31] } {/theRegisters/\registers_reg[24][3] } {/theRegisters/\registers_reg[24][4] } {/theRegisters/\registers_reg[24][5] } {/theRegisters/\registers_reg[24][6] } {/theRegisters/\registers_reg[24][7] } {/theRegisters/\registers_reg[24][8] } {/theRegisters/\registers_reg[24][9] } {/theRegisters/\registers_reg[25][0] } {/theRegisters/\registers_reg[25][10] } {/theRegisters/\registers_reg[25][11] } {/theRegisters/\registers_reg[25][12] } {/theRegisters/\registers_reg[25][13] } {/theRegisters/\registers_reg[25][14] } {/theRegisters/\registers_reg[25][15] } {/theRegisters/\registers_reg[25][16] } {/theRegisters/\registers_reg[25][17] } {/theRegisters/\registers_reg[25][18] } {/theRegisters/\registers_reg[25][19] } {/theRegisters/\registers_reg[25][1] } {/theRegisters/\registers_reg[25][20] } {/theRegisters/\registers_reg[25][21] } {/theRegisters/\registers_reg[25][22] } {/theRegisters/\registers_reg[25][23] } {/theRegisters/\registers_reg[25][24] } {/theRegisters/\registers_reg[25][25] } {/theRegisters/\registers_reg[25][26] } {/theRegisters/\registers_reg[25][27] } {/theRegisters/\registers_reg[25][28] } {/theRegisters/\registers_reg[25][29] } {/theRegisters/\registers_reg[25][2] } {/theRegisters/\registers_reg[25][30] } {/theRegisters/\registers_reg[25][31] } {/theRegisters/\registers_reg[25][3] } {/theRegisters/\registers_reg[25][4] } {/theRegisters/\registers_reg[25][5] } {/theRegisters/\registers_reg[25][6] } {/theRegisters/\registers_reg[25][7] } {/theRegisters/\registers_reg[25][8] } {/theRegisters/\registers_reg[25][9] } {/theRegisters/\registers_reg[26][0] } {/theRegisters/\registers_reg[26][10] } {/theRegisters/\registers_reg[26][11] } {/theRegisters/\registers_reg[26][12] } {/theRegisters/\registers_reg[26][13] } {/theRegisters/\registers_reg[26][14] } {/theRegisters/\registers_reg[26][15] } {/theRegisters/\registers_reg[26][16] } {/theRegisters/\registers_reg[26][17] } {/theRegisters/\registers_reg[26][18] } {/theRegisters/\registers_reg[26][19] } {/theRegisters/\registers_reg[26][1] } {/theRegisters/\registers_reg[26][20] } {/theRegisters/\registers_reg[26][21] } {/theRegisters/\registers_reg[26][22] } {/theRegisters/\registers_reg[26][23] } {/theRegisters/\registers_reg[26][24] } {/theRegisters/\registers_reg[26][25] } {/theRegisters/\registers_reg[26][26] } {/theRegisters/\registers_reg[26][27] } {/theRegisters/\registers_reg[26][28] } {/theRegisters/\registers_reg[26][29] } {/theRegisters/\registers_reg[26][2] } {/theRegisters/\registers_reg[26][30] } {/theRegisters/\registers_reg[26][31] } {/theRegisters/\registers_reg[26][3] } {/theRegisters/\registers_reg[26][4] } {/theRegisters/\registers_reg[26][5] } {/theRegisters/\registers_reg[26][6] } {/theRegisters/\registers_reg[26][7] } {/theRegisters/\registers_reg[26][8] } {/theRegisters/\registers_reg[26][9] } {/theRegisters/\registers_reg[27][0] } {/theRegisters/\registers_reg[27][10] } {/theRegisters/\registers_reg[27][11] } {/theRegisters/\registers_reg[27][12] } {/theRegisters/\registers_reg[27][13] } {/theRegisters/\registers_reg[27][14] } {/theRegisters/\registers_reg[27][15] } {/theRegisters/\registers_reg[27][16] } {/theRegisters/\registers_reg[27][17] } {/theRegisters/\registers_reg[27][18] } {/theRegisters/\registers_reg[27][19] } {/theRegisters/\registers_reg[27][1] } {/theRegisters/\registers_reg[27][20] } {/theRegisters/\registers_reg[27][21] } {/theRegisters/\registers_reg[27][22] } {/theRegisters/\registers_reg[27][23] } {/theRegisters/\registers_reg[27][24] } {/theRegisters/\registers_reg[27][25] } {/theRegisters/\registers_reg[27][26] } {/theRegisters/\registers_reg[27][27] } {/theRegisters/\registers_reg[27][28] } {/theRegisters/\registers_reg[27][29] } {/theRegisters/\registers_reg[27][2] } {/theRegisters/\registers_reg[27][30] } {/theRegisters/\registers_reg[27][31] } {/theRegisters/\registers_reg[27][3] } {/theRegisters/\registers_reg[27][4] } {/theRegisters/\registers_reg[27][5] } {/theRegisters/\registers_reg[27][6] } {/theRegisters/\registers_reg[27][7] } {/theRegisters/\registers_reg[27][8] } {/theRegisters/\registers_reg[27][9] } {/theRegisters/\registers_reg[28][0] } {/theRegisters/\registers_reg[28][10] } {/theRegisters/\registers_reg[28][11] } {/theRegisters/\registers_reg[28][12] } {/theRegisters/\registers_reg[28][13] } {/theRegisters/\registers_reg[28][14] } {/theRegisters/\registers_reg[28][15] } {/theRegisters/\registers_reg[28][16] } {/theRegisters/\registers_reg[28][17] } {/theRegisters/\registers_reg[28][18] } {/theRegisters/\registers_reg[28][19] } {/theRegisters/\registers_reg[28][1] } {/theRegisters/\registers_reg[28][20] } {/theRegisters/\registers_reg[28][21] } {/theRegisters/\registers_reg[28][22] } {/theRegisters/\registers_reg[28][23] } {/theRegisters/\registers_reg[28][24] } {/theRegisters/\registers_reg[28][25] } {/theRegisters/\registers_reg[28][26] } {/theRegisters/\registers_reg[28][27] } {/theRegisters/\registers_reg[28][28] } {/theRegisters/\registers_reg[28][29] } {/theRegisters/\registers_reg[28][2] } {/theRegisters/\registers_reg[28][30] } {/theRegisters/\registers_reg[28][31] } {/theRegisters/\registers_reg[28][3] } {/theRegisters/\registers_reg[28][4] } {/theRegisters/\registers_reg[28][5] } {/theRegisters/\registers_reg[28][6] } {/theRegisters/\registers_reg[28][7] } {/theRegisters/\registers_reg[28][8] } {/theRegisters/\registers_reg[28][9] } {/theRegisters/\registers_reg[29][0] } {/theRegisters/\registers_reg[29][10] } {/theRegisters/\registers_reg[29][11] } {/theRegisters/\registers_reg[29][12] } {/theRegisters/\registers_reg[29][13] } {/theRegisters/\registers_reg[29][14] } {/theRegisters/\registers_reg[29][15] } {/theRegisters/\registers_reg[29][16] } {/theRegisters/\registers_reg[29][17] } {/theRegisters/\registers_reg[29][18] } {/theRegisters/\registers_reg[29][19] } {/theRegisters/\registers_reg[29][1] } {/theRegisters/\registers_reg[29][20] } {/theRegisters/\registers_reg[29][21] } {/theRegisters/\registers_reg[29][22] } {/theRegisters/\registers_reg[29][23] } {/theRegisters/\registers_reg[29][24] } {/theRegisters/\registers_reg[29][25] } {/theRegisters/\registers_reg[29][26] } {/theRegisters/\registers_reg[29][27] } {/theRegisters/\registers_reg[29][28] } {/theRegisters/\registers_reg[29][29] } {/theRegisters/\registers_reg[29][2] } {/theRegisters/\registers_reg[29][30] } {/theRegisters/\registers_reg[29][31] } {/theRegisters/\registers_reg[29][3] } {/theRegisters/\registers_reg[29][4] } {/theRegisters/\registers_reg[29][5] } {/theRegisters/\registers_reg[29][6] } {/theRegisters/\registers_reg[29][7] } {/theRegisters/\registers_reg[29][8] } {/theRegisters/\registers_reg[29][9] } {/theRegisters/\registers_reg[2][0] } {/theRegisters/\registers_reg[2][10] } {/theRegisters/\registers_reg[2][11] } {/theRegisters/\registers_reg[2][12] } {/theRegisters/\registers_reg[2][13] } {/theRegisters/\registers_reg[2][14] } {/theRegisters/\registers_reg[2][15] } {/theRegisters/\registers_reg[2][16] } {/theRegisters/\registers_reg[2][17] } {/theRegisters/\registers_reg[2][18] } {/theRegisters/\registers_reg[2][19] } {/theRegisters/\registers_reg[2][1] } {/theRegisters/\registers_reg[2][20] } {/theRegisters/\registers_reg[2][21] } {/theRegisters/\registers_reg[2][22] } {/theRegisters/\registers_reg[2][23] } {/theRegisters/\registers_reg[2][24] } {/theRegisters/\registers_reg[2][25] } {/theRegisters/\registers_reg[2][26] } {/theRegisters/\registers_reg[2][27] } {/theRegisters/\registers_reg[2][28] } {/theRegisters/\registers_reg[2][29] } {/theRegisters/\registers_reg[2][2] } {/theRegisters/\registers_reg[2][30] } {/theRegisters/\registers_reg[2][31] } {/theRegisters/\registers_reg[2][3] } {/theRegisters/\registers_reg[2][4] } {/theRegisters/\registers_reg[2][5] } {/theRegisters/\registers_reg[2][6] } {/theRegisters/\registers_reg[2][7] } {/theRegisters/\registers_reg[2][8] } {/theRegisters/\registers_reg[2][9] } {/theRegisters/\registers_reg[30][0] } {/theRegisters/\registers_reg[30][10] } {/theRegisters/\registers_reg[30][11] } {/theRegisters/\registers_reg[30][12] } {/theRegisters/\registers_reg[30][13] } {/theRegisters/\registers_reg[30][14] } {/theRegisters/\registers_reg[30][15] } {/theRegisters/\registers_reg[30][16] } {/theRegisters/\registers_reg[30][17] } {/theRegisters/\registers_reg[30][18] } {/theRegisters/\registers_reg[30][19] } {/theRegisters/\registers_reg[30][1] } {/theRegisters/\registers_reg[30][20] } {/theRegisters/\registers_reg[30][21] } {/theRegisters/\registers_reg[30][22] } {/theRegisters/\registers_reg[30][23] } {/theRegisters/\registers_reg[30][24] } {/theRegisters/\registers_reg[30][25] } {/theRegisters/\registers_reg[30][26] } {/theRegisters/\registers_reg[30][27] } {/theRegisters/\registers_reg[30][28] } {/theRegisters/\registers_reg[30][29] } {/theRegisters/\registers_reg[30][2] } {/theRegisters/\registers_reg[30][30] } {/theRegisters/\registers_reg[30][31] } {/theRegisters/\registers_reg[30][3] } {/theRegisters/\registers_reg[30][4] } {/theRegisters/\registers_reg[30][5] } {/theRegisters/\registers_reg[30][6] } {/theRegisters/\registers_reg[30][7] } {/theRegisters/\registers_reg[30][8] } {/theRegisters/\registers_reg[30][9] } " -si_connections "SI_3 " -so_connections "SO_3 " -chain_count 1
// sub-command: create_scan_chain_family scanChain_4 -include_elements "{/theRegisters/\registers_reg[31][0] } {/theRegisters/\registers_reg[31][10] } {/theRegisters/\registers_reg[31][11] } {/theRegisters/\registers_reg[31][12] } {/theRegisters/\registers_reg[31][13] } {/theRegisters/\registers_reg[31][14] } {/theRegisters/\registers_reg[31][15] } {/theRegisters/\registers_reg[31][16] } {/theRegisters/\registers_reg[31][17] } {/theRegisters/\registers_reg[31][18] } {/theRegisters/\registers_reg[31][19] } {/theRegisters/\registers_reg[31][1] } {/theRegisters/\registers_reg[31][20] } {/theRegisters/\registers_reg[31][21] } {/theRegisters/\registers_reg[31][22] } {/theRegisters/\registers_reg[31][23] } {/theRegisters/\registers_reg[31][24] } {/theRegisters/\registers_reg[31][25] } {/theRegisters/\registers_reg[31][26] } {/theRegisters/\registers_reg[31][27] } {/theRegisters/\registers_reg[31][28] } {/theRegisters/\registers_reg[31][29] } {/theRegisters/\registers_reg[31][2] } {/theRegisters/\registers_reg[31][30] } {/theRegisters/\registers_reg[31][31] } {/theRegisters/\registers_reg[31][3] } {/theRegisters/\registers_reg[31][4] } {/theRegisters/\registers_reg[31][5] } {/theRegisters/\registers_reg[31][6] } {/theRegisters/\registers_reg[31][7] } {/theRegisters/\registers_reg[31][8] } {/theRegisters/\registers_reg[31][9] } {/theRegisters/\registers_reg[3][0] } {/theRegisters/\registers_reg[3][10] } {/theRegisters/\registers_reg[3][11] } {/theRegisters/\registers_reg[3][12] } {/theRegisters/\registers_reg[3][13] } {/theRegisters/\registers_reg[3][14] } {/theRegisters/\registers_reg[3][15] } {/theRegisters/\registers_reg[3][16] } {/theRegisters/\registers_reg[3][17] } {/theRegisters/\registers_reg[3][18] } {/theRegisters/\registers_reg[3][19] } {/theRegisters/\registers_reg[3][1] } {/theRegisters/\registers_reg[3][20] } {/theRegisters/\registers_reg[3][21] } {/theRegisters/\registers_reg[3][22] } {/theRegisters/\registers_reg[3][23] } {/theRegisters/\registers_reg[3][24] } {/theRegisters/\registers_reg[3][25] } {/theRegisters/\registers_reg[3][26] } {/theRegisters/\registers_reg[3][27] } {/theRegisters/\registers_reg[3][28] } {/theRegisters/\registers_reg[3][29] } {/theRegisters/\registers_reg[3][2] } {/theRegisters/\registers_reg[3][30] } {/theRegisters/\registers_reg[3][31] } {/theRegisters/\registers_reg[3][3] } {/theRegisters/\registers_reg[3][4] } {/theRegisters/\registers_reg[3][5] } {/theRegisters/\registers_reg[3][6] } {/theRegisters/\registers_reg[3][7] } {/theRegisters/\registers_reg[3][8] } {/theRegisters/\registers_reg[3][9] } {/theRegisters/\registers_reg[4][0] } {/theRegisters/\registers_reg[4][10] } {/theRegisters/\registers_reg[4][11] } {/theRegisters/\registers_reg[4][12] } {/theRegisters/\registers_reg[4][13] } {/theRegisters/\registers_reg[4][14] } {/theRegisters/\registers_reg[4][15] } {/theRegisters/\registers_reg[4][16] } {/theRegisters/\registers_reg[4][17] } {/theRegisters/\registers_reg[4][18] } {/theRegisters/\registers_reg[4][19] } {/theRegisters/\registers_reg[4][1] } {/theRegisters/\registers_reg[4][20] } {/theRegisters/\registers_reg[4][21] } {/theRegisters/\registers_reg[4][22] } {/theRegisters/\registers_reg[4][23] } {/theRegisters/\registers_reg[4][24] } {/theRegisters/\registers_reg[4][25] } {/theRegisters/\registers_reg[4][26] } {/theRegisters/\registers_reg[4][27] } {/theRegisters/\registers_reg[4][28] } {/theRegisters/\registers_reg[4][29] } {/theRegisters/\registers_reg[4][2] } {/theRegisters/\registers_reg[4][30] } {/theRegisters/\registers_reg[4][31] } {/theRegisters/\registers_reg[4][3] } {/theRegisters/\registers_reg[4][4] } {/theRegisters/\registers_reg[4][5] } {/theRegisters/\registers_reg[4][6] } {/theRegisters/\registers_reg[4][7] } {/theRegisters/\registers_reg[4][8] } {/theRegisters/\registers_reg[4][9] } {/theRegisters/\registers_reg[5][0] } {/theRegisters/\registers_reg[5][10] } {/theRegisters/\registers_reg[5][11] } {/theRegisters/\registers_reg[5][12] } {/theRegisters/\registers_reg[5][13] } {/theRegisters/\registers_reg[5][14] } {/theRegisters/\registers_reg[5][15] } {/theRegisters/\registers_reg[5][16] } {/theRegisters/\registers_reg[5][17] } {/theRegisters/\registers_reg[5][18] } {/theRegisters/\registers_reg[5][19] } {/theRegisters/\registers_reg[5][1] } {/theRegisters/\registers_reg[5][20] } {/theRegisters/\registers_reg[5][21] } {/theRegisters/\registers_reg[5][22] } {/theRegisters/\registers_reg[5][23] } {/theRegisters/\registers_reg[5][24] } {/theRegisters/\registers_reg[5][25] } {/theRegisters/\registers_reg[5][26] } {/theRegisters/\registers_reg[5][27] } {/theRegisters/\registers_reg[5][28] } {/theRegisters/\registers_reg[5][29] } {/theRegisters/\registers_reg[5][2] } {/theRegisters/\registers_reg[5][30] } {/theRegisters/\registers_reg[5][31] } {/theRegisters/\registers_reg[5][3] } {/theRegisters/\registers_reg[5][4] } {/theRegisters/\registers_reg[5][5] } {/theRegisters/\registers_reg[5][6] } {/theRegisters/\registers_reg[5][7] } {/theRegisters/\registers_reg[5][8] } {/theRegisters/\registers_reg[5][9] } {/theRegisters/\registers_reg[6][0] } {/theRegisters/\registers_reg[6][10] } {/theRegisters/\registers_reg[6][11] } {/theRegisters/\registers_reg[6][12] } {/theRegisters/\registers_reg[6][13] } {/theRegisters/\registers_reg[6][14] } {/theRegisters/\registers_reg[6][15] } {/theRegisters/\registers_reg[6][16] } {/theRegisters/\registers_reg[6][17] } {/theRegisters/\registers_reg[6][18] } {/theRegisters/\registers_reg[6][19] } {/theRegisters/\registers_reg[6][1] } {/theRegisters/\registers_reg[6][20] } {/theRegisters/\registers_reg[6][21] } {/theRegisters/\registers_reg[6][22] } {/theRegisters/\registers_reg[6][23] } {/theRegisters/\registers_reg[6][24] } {/theRegisters/\registers_reg[6][25] } {/theRegisters/\registers_reg[6][26] } {/theRegisters/\registers_reg[6][27] } {/theRegisters/\registers_reg[6][28] } {/theRegisters/\registers_reg[6][29] } {/theRegisters/\registers_reg[6][2] } {/theRegisters/\registers_reg[6][30] } {/theRegisters/\registers_reg[6][31] } {/theRegisters/\registers_reg[6][3] } {/theRegisters/\registers_reg[6][4] } {/theRegisters/\registers_reg[6][5] } {/theRegisters/\registers_reg[6][6] } {/theRegisters/\registers_reg[6][7] } {/theRegisters/\registers_reg[6][8] } {/theRegisters/\registers_reg[6][9] } {/theRegisters/\registers_reg[7][0] } {/theRegisters/\registers_reg[7][10] } {/theRegisters/\registers_reg[7][11] } {/theRegisters/\registers_reg[7][12] } {/theRegisters/\registers_reg[7][13] } {/theRegisters/\registers_reg[7][14] } {/theRegisters/\registers_reg[7][15] } {/theRegisters/\registers_reg[7][16] } {/theRegisters/\registers_reg[7][17] } {/theRegisters/\registers_reg[7][18] } {/theRegisters/\registers_reg[7][19] } {/theRegisters/\registers_reg[7][1] } {/theRegisters/\registers_reg[7][20] } {/theRegisters/\registers_reg[7][21] } {/theRegisters/\registers_reg[7][22] } {/theRegisters/\registers_reg[7][23] } {/theRegisters/\registers_reg[7][24] } {/theRegisters/\registers_reg[7][25] } {/theRegisters/\registers_reg[7][26] } {/theRegisters/\registers_reg[7][27] } {/theRegisters/\registers_reg[7][28] } {/theRegisters/\registers_reg[7][29] } {/theRegisters/\registers_reg[7][2] } {/theRegisters/\registers_reg[7][30] } {/theRegisters/\registers_reg[7][31] } {/theRegisters/\registers_reg[7][3] } {/theRegisters/\registers_reg[7][4] } {/theRegisters/\registers_reg[7][5] } {/theRegisters/\registers_reg[7][6] } {/theRegisters/\registers_reg[7][7] } {/theRegisters/\registers_reg[7][8] } {/theRegisters/\registers_reg[7][9] } {/theRegisters/\registers_reg[8][0] } {/theRegisters/\registers_reg[8][10] } {/theRegisters/\registers_reg[8][11] } {/theRegisters/\registers_reg[8][12] } {/theRegisters/\registers_reg[8][13] } {/theRegisters/\registers_reg[8][14] } {/theRegisters/\registers_reg[8][15] } {/theRegisters/\registers_reg[8][16] } {/theRegisters/\registers_reg[8][17] } {/theRegisters/\registers_reg[8][18] } {/theRegisters/\registers_reg[8][19] } {/theRegisters/\registers_reg[8][1] } {/theRegisters/\registers_reg[8][20] } {/theRegisters/\registers_reg[8][21] } {/theRegisters/\registers_reg[8][22] } {/theRegisters/\registers_reg[8][23] } {/theRegisters/\registers_reg[8][24] } {/theRegisters/\registers_reg[8][25] } {/theRegisters/\registers_reg[8][26] } {/theRegisters/\registers_reg[8][27] } {/theRegisters/\registers_reg[8][28] } {/theRegisters/\registers_reg[8][29] } {/theRegisters/\registers_reg[8][2] } {/theRegisters/\registers_reg[8][30] } {/theRegisters/\registers_reg[8][31] } {/theRegisters/\registers_reg[8][3] } {/theRegisters/\registers_reg[8][4] } {/theRegisters/\registers_reg[8][5] } {/theRegisters/\registers_reg[8][6] } {/theRegisters/\registers_reg[8][7] } {/theRegisters/\registers_reg[8][8] } {/theRegisters/\registers_reg[8][9] } {/theRegisters/\registers_reg[9][0] } {/theRegisters/\registers_reg[9][10] } {/theRegisters/\registers_reg[9][11] } {/theRegisters/\registers_reg[9][12] } {/theRegisters/\registers_reg[9][13] } {/theRegisters/\registers_reg[9][14] } {/theRegisters/\registers_reg[9][15] } {/theRegisters/\registers_reg[9][16] } {/theRegisters/\registers_reg[9][17] } {/theRegisters/\registers_reg[9][18] } {/theRegisters/\registers_reg[9][19] } {/theRegisters/\registers_reg[9][1] } {/theRegisters/\registers_reg[9][20] } {/theRegisters/\registers_reg[9][21] } {/theRegisters/\registers_reg[9][22] } {/theRegisters/\registers_reg[9][23] } {/theRegisters/\registers_reg[9][24] } {/theRegisters/\registers_reg[9][25] } {/theRegisters/\registers_reg[9][26] } {/theRegisters/\registers_reg[9][27] } {/theRegisters/\registers_reg[9][28] } {/theRegisters/\registers_reg[9][29] } {/theRegisters/\registers_reg[9][2] } {/theRegisters/\registers_reg[9][30] } {/theRegisters/\registers_reg[9][31] } {/theRegisters/\registers_reg[9][3] } {/theRegisters/\registers_reg[9][4] } {/theRegisters/\registers_reg[9][5] } {/theRegisters/\registers_reg[9][6] } {/theRegisters/\registers_reg[9][7] } {/theRegisters/\registers_reg[9][8] } {/theRegisters/\registers_reg[9][9] } " -si_connections "SI_4 " -so_connections "SO_4 " -chain_count 1
// sub-command: analyze_scan_chains
// Chain allocation of 'unwrapped' mode completed:
// 4 distributed chains of size 256
// sub-command: insert_test_logic -write_in_tsdb on
=============================
Test Logic Insertion Summary:
=============================
Structural Data:
----------------
Added top-level port count: 0
Added instance count: 8
Logical Data:
-------------
Added retiming logic count: 4
Added scan chain count (unwrapped): 4
// Warning: Flattened model deleted.
//
// Writing out netlist and related files in /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design
// sub-command: report_scan_chains
===============================
Scan Chains Created by the Tool
===============================
Scan mode 'unwrapped' scan chains:
----------------------------------
Cluster 'scanChain_1' chains:
-----------------------------
chain = scanChain_1 group = dummy input = /SI_1 output = /SO_1 length = 256
Cluster 'scanChain_2' chains:
-----------------------------
chain = scanChain_2 group = dummy input = /SI_2 output = /SO_2 length = 256
Cluster 'scanChain_3' chains:
-----------------------------
chain = scanChain_3 group = dummy input = /SI_3 output = /SO_3 length = 256
Cluster 'scanChain_4' chains:
-----------------------------
chain = scanChain_4 group = dummy input = /SI_4 output = /SO_4 length = 256
// sub-command: write_scan_order /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/cpu.scandef -use_escaping_rule Lefdef -replace
// sub-command: write_design -output_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/post_scan.v -replace
// command: exit
**************************************************************************************************************************************************************************************
TESSENT EXECUTION ENDS HERE !
**************************************************************************************************************************************************************************************
Dumping current design to /tmp/oasys.2483642/dft_eco/cpu
> write_db /tmp/oasys.2483642/dft_eco/cpu
info: Target library/cell information has changed that further may change timing results. [TA-159]
info: Successfully traced scan chain (scan_in: 'SI_1', scan_out: 'SO_1' with 258 elements ) [DFT-354]
info: Successfully traced scan chain (scan_in: 'SI_2', scan_out: 'SO_2' with 258 elements ) [DFT-354]
info: Successfully traced scan chain (scan_in: 'SI_3', scan_out: 'SO_3' with 258 elements ) [DFT-354]
info: Successfully traced scan chain (scan_in: 'SI_4', scan_out: 'SO_4' with 258 elements ) [DFT-354]
> write_db ./output/odb/riscv.tessent_post_scan.odb
> write_verilog ./output/riscv.tessent_post_scan.v
info: writing Verilog file './output/riscv.tessent_post_scan.v' for module 'cpu' [WRITE-100]
----------report_power----------------
> report_power
Report Power (instances with prefix '*' are included in total) :
-----+----------------------------------------+--------------------+---------------------+-------------------+-----------------
| Instance | Internal Power (uW)| Switching Power (uW)| Leakage Power (uW)| Total Power (uW)
-----+----------------------------------------+--------------------+---------------------+-------------------+-----------------
1 |*theMem | 4965.347656| 97.271141| 528.368530| 5590.987793
2 |*theRegisters | 2937.885254| 65.439415| 75.000534| 3078.325195
3 |*theDecoder | 3306.815674| 29.696104| 69.466927| 3405.978516
4 |*thePC_i_0 | 102.036263| 0.516853| 0.818020| 103.371140
5 |*thePC_CurrentPC_reg[31] | 6.132826| 0.115208| 0.000019| 6.248054
6 |*thePC_CurrentPC_reg[30] | 6.132829| 0.122289| 0.000019| 6.255136
7 |*thePC_CurrentPC_reg[29] | 6.132829| 0.122289| 0.000019| 6.255136
8 |*thePC_CurrentPC_reg[28] | 6.132829| 0.122289| 0.000019| 6.255136
9 |*thePC_CurrentPC_reg[27] | 6.132829| 0.122289| 0.000019| 6.255136
10 |*thePC_CurrentPC_reg[26] | 6.132829| 0.122289| 0.000019| 6.255136
11 |*thePC_CurrentPC_reg[25] | 6.132829| 0.122289| 0.000019| 6.255136
12 |*thePC_CurrentPC_reg[24] | 6.132829| 0.122289| 0.000019| 6.255136
13 |*thePC_CurrentPC_reg[23] | 6.132829| 0.122289| 0.000019| 6.255136
14 |*thePC_CurrentPC_reg[22] | 6.132829| 0.122289| 0.000019| 6.255136
15 |*thePC_CurrentPC_reg[21] | 6.135628| 0.207666| 0.000019| 6.343312
16 |*thePC_CurrentPC_reg[20] | 6.132829| 0.122289| 0.000019| 6.255136
17 |*thePC_CurrentPC_reg[19] | 6.132828| 0.121340| 0.000019| 6.254188
18 |*thePC_CurrentPC_reg[18] | 6.132828| 0.121340| 0.000019| 6.254188
19 |*thePC_CurrentPC_reg[17] | 6.132828| 0.121340| 0.000019| 6.254188
20 |*thePC_CurrentPC_reg[16] | 6.132828| 0.121340| 0.000019| 6.254188
21 |*thePC_CurrentPC_reg[15] | 6.132826| 0.115029| 0.000019| 6.247873
22 |*thePC_CurrentPC_reg[14] | 6.132828| 0.121340| 0.000019| 6.254188
23 |*thePC_CurrentPC_reg[13] | 6.135591| 0.206718| 0.000019| 6.342327
24 |*thePC_CurrentPC_reg[12] | 6.132828| 0.121340| 0.000019| 6.254188
25 |*thePC_CurrentPC_reg[11] | 6.132828| 0.120392| 0.000019| 6.253239
26 |*thePC_CurrentPC_reg[10] | 6.132827| 0.115675| 0.000019| 6.248520
27 |*thePC_CurrentPC_reg[9] | 6.132827| 0.115675| 0.000019| 6.248520
28 |*thePC_CurrentPC_reg[8] | 6.132827| 0.115675| 0.000019| 6.248520
29 |*thePC_CurrentPC_reg[7] | 6.132825| 0.109358| 0.000019| 6.242202
30 |*thePC_CurrentPC_reg[6] | 6.132825| 0.109358| 0.000019| 6.242202
31 |*thePC_CurrentPC_reg[5] | 6.132825| 0.109358| 0.000019| 6.242202
32 |*thePC_CurrentPC_reg[4] | 6.132825| 0.109358| 0.000019| 6.242202
33 |*thePC_CurrentPC_reg[3] | 6.132825| 0.109358| 0.000019| 6.242202
34 |*thePC_CurrentPC_reg[2] | 6.136212| 0.222482| 0.000019| 6.358713
35 |*thePC_CurrentPC_reg[1] | 6.132825| 0.110713| 0.000019| 6.243557
36 |*thePC_CurrentPC_reg[0] | 6.132828| 0.121456| 0.000019| 6.254303
37 |*i_0_0_0 | 3.636180| 0.005795| 0.056141| 3.698117
38 |*i_0_0_1 | 3.630034| 0.075574| 0.049831| 3.755438
39 |*i_0_0_2 | 3.589001| 0.005720| 0.056141| 3.650862
40 |*i_0_0_3 | 3.579433| 0.074593| 0.049831| 3.703857
41 |*i_0_0_4 | 4.765921| 0.005811| 0.038697| 4.810430
42 |*i_0_0_5 | 4.765921| 0.005811| 0.038697| 4.810430
43 |*i_0_0_6 | 4.765921| 0.005811| 0.038697| 4.810430
44 |*i_0_0_7 | 4.765921| 0.005811| 0.038697| 4.810430
45 |*i_0_0_8 | 4.765921| 0.005811| 0.038697| 4.810430
46 |*i_0_0_9 | 4.765921| 0.005811| 0.038697| 4.810430
47 |*i_0_0_10 | 4.760734| 0.005811| 0.038697| 4.805242
48 |*i_0_0_11 | 4.760734| 0.005811| 0.038697| 4.805242
49 |*i_0_0_12 | 4.760734| 0.005811| 0.038697| 4.805242
50 |*i_0_0_13 | 4.760734| 0.005811| 0.038697| 4.805242
51 |*i_0_0_14 | 4.760734| 0.005811| 0.038697| 4.805242
52 |*i_0_0_15 | 3.589408| 0.005721| 0.056141| 3.651270
53 |*i_0_0_16 | 3.579309| 0.074602| 0.049831| 3.703742
54 |*i_0_0_17 | 3.589739| 0.005721| 0.056141| 3.651601
55 |*i_0_0_18 | 3.579648| 0.074608| 0.049831| 3.704087
56 |*i_0_0_19 | 3.590052| 0.005722| 0.056141| 3.651915
57 |*i_0_0_20 | 3.579969| 0.074615| 0.049831| 3.704415
58 |*i_0_0_21 | 3.590306| 0.005722| 0.056141| 3.652169
59 |*i_0_0_22 | 3.580231| 0.074620| 0.049831| 3.704682
60 |*i_0_0_23 | 3.590506| 0.005722| 0.056141| 3.652370
61 |*i_0_0_24 | 3.580436| 0.074625| 0.049831| 3.704891
62 |*i_0_0_25 | 3.590656| 0.005723| 0.056141| 3.652520
63 |*i_0_0_26 | 3.580589| 0.074627| 0.049831| 3.705047
64 |*i_0_0_27 | 3.590823| 0.005723| 0.056141| 3.652687
65 |*i_0_0_28 | 3.580760| 0.074631| 0.049831| 3.705222
66 |*i_0_0_29 | 3.590933| 0.005723| 0.056141| 3.652797
67 |*i_0_0_30 | 3.580874| 0.074633| 0.049831| 3.705338
68 |*i_0_0_31 | 3.590987| 0.005723| 0.056141| 3.652852
69 |*i_0_0_32 | 3.580929| 0.074634| 0.049831| 3.705395
70 |*i_0_0_33 | 3.591065| 0.005723| 0.056141| 3.652930
71 |*i_0_0_34 | 3.581009| 0.074636| 0.049831| 3.705476
72 |*i_0_0_35 | 3.591195| 0.005724| 0.056141| 3.653060
73 |*i_0_0_36 | 3.581142| 0.074639| 0.049831| 3.705612
74 |*i_0_0_37 | 3.591303| 0.005724| 0.056141| 3.653168
75 |*i_0_0_38 | 3.581253| 0.074641| 0.049831| 3.705725
76 |*i_0_0_39 | 3.591386| 0.005724| 0.056141| 3.653251
77 |*i_0_0_40 | 3.581338| 0.074643| 0.049831| 3.705812
78 |*i_0_0_41 | 3.591435| 0.005724| 0.056141| 3.653301
79 |*i_0_0_42 | 3.581389| 0.074644| 0.049831| 3.705863
80 |*i_0_0_43 | 3.591419| 0.005724| 0.056141| 3.653284
81 |*i_0_0_44 | 3.581372| 0.074644| 0.049831| 3.705847
82 |*i_0_0_45 | 3.591433| 0.005724| 0.056141| 3.653298
83 |*i_0_0_46 | 3.581386| 0.074644| 0.049831| 3.705861
84 |*i_0_0_47 | 3.591558| 0.005724| 0.056141| 3.653424
85 |*i_0_0_48 | 3.581515| 0.074646| 0.049831| 3.705992
86 |*i_0_0_49 | 3.591676| 0.005724| 0.056141| 3.653541
87 |*i_0_0_50 | 3.581635| 0.074649| 0.049831| 3.706115
88 |*i_0_0_51 | 3.591723| 0.005724| 0.056141| 3.653588
89 |*i_0_0_52 | 3.581872| 0.074650| 0.049831| 3.706352
90 |*i_0_0_53 | 0.270481| 0.031764| 0.181711| 0.483956
91 |*i_0_0_54 | 8.109213| 0.417922| 0.187759| 8.714894
92 |*i_0_0_55 | 4.662969| 0.392350| 0.167543| 5.222862
93 |*i_0_0_56 | 4.661758| 0.392909| 0.167809| 5.222477
94 |*i_0_0_57 | 4.661533| 0.392163| 0.167455| 5.221151
95 |*i_0_0_58 | 4.661815| 0.393097| 0.167897| 5.222809
96 |*i_0_0_59 | 4.661477| 0.391976| 0.167366| 5.220819
97 |*i_0_0_60 | 4.661870| 0.393283| 0.167986| 5.223139
98 |*i_0_0_61 | 4.263187| 0.064498| 0.029698| 4.357384
99 |*i_0_0_62 | 4.263187| 0.064498| 0.029698| 4.357384
100 |*i_0_0_63 | 4.263187| 0.064498| 0.029698| 4.357384
101 |*i_0_0_64 | 4.263187| 0.064498| 0.029698| 4.357384
102 |*i_0_0_65 | 4.263187| 0.064498| 0.029698| 4.357384
103 |*i_0_0_66 | 892.076904| 9.773184| 0.224563| 902.074707
104 |*tessent_persistent_cell_buf_extsi1225_i| 12.245425| 0.023904| 0.084228| 12.353557
105 | | | | |
106 |*TOTAL | 12673.423828| 211.665421| 678.138367| 13563.228516
-----+----------------------------------------+--------------------+---------------------+-------------------+-----------------
----------report_path_groups----------------
> report_path_groups
Report Path Groups:
-----+-------+------+---------+---------
| Path |Weight|Critical |Worst
| Group | |Range(ps)|Slack(ps)
-----+-------+------+---------+---------
1 |default| 1.000| 0.0| 18131.2
2 |I2R | 1.000| 0.0|<ill>
3 |I2O | 1.000| 0.0|<ill>
4 |R2O | 1.000| 0.0| 36309.8
-----+-------+------+---------+---------
----------report_scan_chains----------------
> report_scan_chains
Report ScanChains:
--------+-----------+--------------+--------+-----------+-----------+--------------+------------------+--------+--------+---------+-----------+----------
Index | Chain | ScanInstance | Length | TestClock | ClockEdge | Comp. Chains | Max Comp. Length | Lockup | ScanIn | ScanOut | Partition | ScanMode
--------+-----------+--------------+--------+-----------+-----------+--------------+------------------+--------+--------+---------+-----------+----------
1|scanChain_1| 258 | 256|clk_25mhz |rise | - | - | 1|SI_1 |SO_1 | - |
2|scanChain_2| 258 | 256|clk_25mhz |rise | - | - | 1|SI_2 |SO_2 | - |
3|scanChain_3| 258 | 256|clk_25mhz |rise | - | - | 1|SI_3 |SO_3 | - |
4|scanChain_4| 258 | 256|clk_25mhz |rise | - | - | 1|SI_4 |SO_4 | - |
--------+-----------+--------------+--------+-----------+-----------+--------------+------------------+--------+--------+---------+-----------+----------
----------report_timing----------------
> report_timing
Report for group default
--------------------------------------------------------------------------------------------------------------------------------------
Startpoint: theMem/IRData_reg[18]/Q
(Clocked by clk_25mhz R)
Endpoint: theMem/mem_addr_reg[5]/D
(Clocked by clk_25mhz F)
Path Group: default
Data required time: 19371.2
(Clock shift: 20000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Setup time: 128.8)
Data arrival time: 1240.0
Slack: 18131.2
Logic depth: 46
--------------------------------------------------------------------------------------------------------------------------------------
Arrival Arc Net Net Total fan-
Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location
(ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um)
--------------------------------------------------------------------------------------------------------------------------------------
clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 101, 0
theMem/IRData_reg[18]/CK->Q
DFF_X1_LVT* rr 106.0 106.0 106.0 0.0 100.0 15.2 77.1 10 175, 106
theRegisters/i_1_0_1371/A->ZN
INV_X8_LVT rf 108.7 2.7 2.7 0.0 10.2 2.1 13.2 3 168, 158
theRegisters/i_1_0_1339/A2->ZN
NAND3_X4_LVT fr 122.7 14.0 14.0 0.0 1.0 2.5 17.5 4 168, 158
theRegisters/i_1_0_1321/A2->ZN
NOR2_X4_LVT* rf 141.6 19.0 19.0 0.0 12.1 29.7 130.1 32 168, 158
theRegisters/i_1_0_722/B1->ZN
AOI22_X4_LVT* fr 186.0 44.3 44.3 0.0 10.2 0.7 23.4 1 168, 158
theRegisters/i_1_0_721/A->ZN
INV_X8_LVT rf 188.1 2.1 2.1 0.0 10.2 0.8 3.0 1 168, 158
theRegisters/i_1_0_718/A->ZN
AOI221_X2_LVT fr 245.4 57.3 57.3 0.0 0.6 0.9 4.4 1 168, 158
theRegisters/i_1_0_716/A3->ZN
NAND4_X4_LVT rf 260.8 15.4 15.4 0.0 34.6 0.9 3.1 1 168, 158
theRegisters/i_1_0_715/A->ZN
AOI221_X2_LVT fr 318.1 57.4 57.4 0.0 6.8 0.9 4.3 1 168, 158
theRegisters/i_1_0_704/A2->ZN
NAND4_X4_LVT* rf 342.3 24.2 24.2 0.0 34.4 14.1 24.9 3 168, 158
theDecoder/i_0_133/C2->ZN
AOI222_X4_LVT fr 452.6 110.3 110.3 0.0 10.2 0.8 23.5 1 129, 89
theDecoder/i_0_132/A->ZN INV_X32_LVT rf 455.7 3.1 3.1 0.0 10.9 5.4 65.3 7 129, 89
theDecoder/theALU/i_0_706/B1->ZN
OAI22_X4_LVT* fr 498.9 43.2 43.2 0.0 1.4 1.5 25.9 2 129, 89
theDecoder/theALU/i_0_705/A->ZN
INV_X8_LVT rf 501.1 2.2 2.2 0.0 10.2 0.6 4.2 1 129, 89
theDecoder/theALU/i_0_42/A->ZN
OAI21_X2_LVT fr 510.2 9.1 9.1 0.0 0.6 0.8 2.5 1 129, 89
theDecoder/theALU/i_0_40/C1->ZN
AOI211_X2_LVT rf 515.8 5.6 5.6 0.0 11.6 0.8 2.9 1 129, 89
theDecoder/theALU/i_0_39/B->ZN
AOI211_X2_LVT fr 563.3 47.4 47.4 0.0 3.3 0.9 3.0 1 129, 89
theDecoder/theALU/i_0_38/B2->ZN
OAI222_X2_LVT rf 580.2 16.9 16.9 0.0 27.7 0.9 2.9 1 129, 89
theDecoder/theALU/i_0_37/C2->ZN
AOI221_X2_LVT fr 624.0 43.8 43.8 0.0 8.4 0.9 4.2 1 129, 89
theDecoder/theALU/i_0_35/B1->ZN
OAI22_X4_LVT* rf 637.9 13.9 13.9 0.0 34.0 0.7 23.4 1 129, 89
theDecoder/theALU/i_0_34/A->ZN
INV_X8_LVT fr 642.4 4.5 4.5 0.0 10.2 0.6 4.1 1 129, 89
theDecoder/theALU/i_0_33/A->ZN
AOI21_X4_LVT rf 645.0 2.6 2.6 0.0 2.4 0.8 3.0 1 129, 89
theDecoder/theALU/i_0_32/C2->ZN
OAI222_X2_LVT fr 683.5 38.5 38.5 0.0 2.6 0.9 3.3 1 129, 89
theDecoder/theALU/i_0_31/A->ZN
OAI221_X2_LVT rf 699.6 16.0 16.0 0.0 29.2 0.8 4.0 1 129, 89
theDecoder/theALU/i_0_28/B1->ZN
AOI21_X4_LVT fr 715.0 15.5 15.5 0.0 8.2 0.8 3.0 1 129, 89
theDecoder/theALU/i_0_27/A->ZN
AOI221_X2_LVT rf 719.3 4.2 4.2 0.0 13.5 0.9 2.9 1 129, 89
theDecoder/theALU/i_0_26/B->ZN
AOI211_X2_LVT fr 771.5 52.2 52.2 0.0 5.3 0.8 4.6 1 129, 89
theDecoder/theALU/i_0_25/B2->ZN
OAI22_X2_LVT rf 781.1 9.7 9.7 0.0 31.8 0.8 2.7 1 129, 89
theDecoder/theALU/i_0_24/C2->ZN
AOI211_X2_LVT fr 815.5 34.4 34.4 0.0 4.0 0.9 3.1 1 129, 89
theDecoder/theALU/i_0_23/A->ZN
AOI221_X2_LVT rf 821.3 5.8 5.8 0.0 27.8 0.9 3.1 1 129, 89
theDecoder/theALU/i_0_22/A->ZN
AOI221_X2_LVT fr 874.9 53.7 53.7 0.0 5.4 0.9 3.1 1 129, 89
theDecoder/theALU/i_0_21/A->ZN
AOI221_X2_LVT rf 881.0 6.1 6.1 0.0 31.2 0.9 3.1 1 129, 89
theDecoder/theALU/i_0_20/C2->ZN
OAI222_X2_LVT fr 919.8 38.8 38.8 0.0 5.4 0.9 3.3 1 129, 89
theDecoder/theALU/i_0_19/A->ZN
OAI221_X2_LVT rf 936.3 16.6 16.6 0.0 29.2 0.9 4.7 1 129, 89
theDecoder/theALU/i_0_18/B2->ZN
AOI22_X4_LVT fr 966.6 30.3 30.3 0.0 8.6 0.8 4.4 1 129, 89
theDecoder/theALU/i_0_17/B2->ZN
OAI21_X4_LVT rf 973.1 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89
theDecoder/theALU/i_0_16/A->ZN
OAI21_X4_LVT fr 982.8 9.8 9.8 0.0 3.6 0.7 3.9 1 129, 89
theDecoder/theALU/i_0_13/B1->ZN
AOI21_X4_LVT rf 988.1 5.3 5.3 0.0 12.5 0.8 4.4 1 129, 89
theDecoder/theALU/i_0_12/A4->ZN
NOR4_X2_LVT fr 1044.5 56.5 56.5 0.0 2.9 0.8 2.8 1 129, 89
theDecoder/theALU/i_0_0/A3->ZN
OR3_X4_LVT rr 1062.9 18.3 18.3 0.0 29.1 0.7 18.9 2 129, 89
theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1069.5 6.7 6.7 0.0 9.3 0.7 4.3 1 129, 89
theDecoder/i_0_113/B1->ZN
AOI22_X4_LVT fr 1096.0 26.5 26.5 0.0 5.1 0.8 4.4 1 129, 89
theDecoder/i_0_111/A2->ZN
AOI22_X4_LVT rf 1102.4 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89
theDecoder/i_0_110/A2->ZN
NAND2_X4_LVT* fr 1121.6 19.2 19.2 0.0 4.4 9.0 37.6 13 129, 89
i_0_0_60/S->Z MUX2_X2_LVT* rf 1190.2 68.6 68.6 0.0 10.2 32.0 87.6 3 129, 89
theMem/i_0_0_11/B2->ZN AOI22_X4_LVT* fr 1238.0 47.8 47.8 0.0 10.2 0.7 23.4 1 175, 106
theMem/i_0_0_10/A->ZN INV_X8_LVT rf 1240.0 2.0 2.0 0.0 10.2 0.7 1.7 1 175, 106
theMem/mem_addr_reg[5]/D DFF_X1_LVT f 1240.0 0.0 0.0 0.5 175, 106
--------------------------------------------------------------------------------------------------------------------------------------
Report for group I2R
Report for group I2O
Report for group R2O
--------------------------------------------------------------------------------------------------------------------------------------
Startpoint: theMem/IRData_reg[18]/Q
(Clocked by clk_25mhz R)
Endpoint: led[7]
(Clocked by clk_25mhz R)
Path Group: R2O
Data required time: 37500.0
(Clock shift: 40000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Out delay: 2000.0)
Data arrival time: 1190.2
Slack: 36309.8
Logic depth: 44
--------------------------------------------------------------------------------------------------------------------------------------
Arrival Arc Net Net Total fan-
Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location
(ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um)
--------------------------------------------------------------------------------------------------------------------------------------
clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 101, 0
theMem/IRData_reg[18]/CK->Q
DFF_X1_LVT* rr 106.0 106.0 106.0 0.0 100.0 15.2 77.1 10 175, 106
theRegisters/i_1_0_1371/A->ZN
INV_X8_LVT rf 108.7 2.7 2.7 0.0 10.2 2.1 13.2 3 168, 158
theRegisters/i_1_0_1339/A2->ZN
NAND3_X4_LVT fr 122.7 14.0 14.0 0.0 1.0 2.5 17.5 4 168, 158
theRegisters/i_1_0_1321/A2->ZN
NOR2_X4_LVT* rf 141.6 19.0 19.0 0.0 12.1 29.7 130.1 32 168, 158
theRegisters/i_1_0_722/B1->ZN
AOI22_X4_LVT* fr 186.0 44.3 44.3 0.0 10.2 0.7 23.4 1 168, 158
theRegisters/i_1_0_721/A->ZN
INV_X8_LVT rf 188.1 2.1 2.1 0.0 10.2 0.8 3.0 1 168, 158
theRegisters/i_1_0_718/A->ZN
AOI221_X2_LVT fr 245.4 57.3 57.3 0.0 0.6 0.9 4.4 1 168, 158
theRegisters/i_1_0_716/A3->ZN
NAND4_X4_LVT rf 260.8 15.4 15.4 0.0 34.6 0.9 3.1 1 168, 158
theRegisters/i_1_0_715/A->ZN
AOI221_X2_LVT fr 318.1 57.4 57.4 0.0 6.8 0.9 4.3 1 168, 158
theRegisters/i_1_0_704/A2->ZN
NAND4_X4_LVT* rf 342.3 24.2 24.2 0.0 34.4 14.1 24.9 3 168, 158
theDecoder/i_0_133/C2->ZN
AOI222_X4_LVT fr 452.6 110.3 110.3 0.0 10.2 0.8 23.5 1 129, 89
theDecoder/i_0_132/A->ZN INV_X32_LVT rf 455.7 3.1 3.1 0.0 10.9 5.4 65.3 7 129, 89
theDecoder/theALU/i_0_706/B1->ZN
OAI22_X4_LVT* fr 498.9 43.2 43.2 0.0 1.4 1.5 25.9 2 129, 89
theDecoder/theALU/i_0_705/A->ZN
INV_X8_LVT rf 501.1 2.2 2.2 0.0 10.2 0.6 4.2 1 129, 89
theDecoder/theALU/i_0_42/A->ZN
OAI21_X2_LVT fr 510.2 9.1 9.1 0.0 0.6 0.8 2.5 1 129, 89
theDecoder/theALU/i_0_40/C1->ZN
AOI211_X2_LVT rf 515.8 5.6 5.6 0.0 11.6 0.8 2.9 1 129, 89
theDecoder/theALU/i_0_39/B->ZN
AOI211_X2_LVT fr 563.3 47.4 47.4 0.0 3.3 0.9 3.0 1 129, 89
theDecoder/theALU/i_0_38/B2->ZN
OAI222_X2_LVT rf 580.2 16.9 16.9 0.0 27.7 0.9 2.9 1 129, 89
theDecoder/theALU/i_0_37/C2->ZN
AOI221_X2_LVT fr 624.0 43.8 43.8 0.0 8.4 0.9 4.2 1 129, 89
theDecoder/theALU/i_0_35/B1->ZN
OAI22_X4_LVT* rf 637.9 13.9 13.9 0.0 34.0 0.7 23.4 1 129, 89
theDecoder/theALU/i_0_34/A->ZN
INV_X8_LVT fr 642.4 4.5 4.5 0.0 10.2 0.6 4.1 1 129, 89
theDecoder/theALU/i_0_33/A->ZN
AOI21_X4_LVT rf 645.0 2.6 2.6 0.0 2.4 0.8 3.0 1 129, 89
theDecoder/theALU/i_0_32/C2->ZN
OAI222_X2_LVT fr 683.5 38.5 38.5 0.0 2.6 0.9 3.3 1 129, 89
theDecoder/theALU/i_0_31/A->ZN
OAI221_X2_LVT rf 699.6 16.0 16.0 0.0 29.2 0.8 4.0 1 129, 89
theDecoder/theALU/i_0_28/B1->ZN
AOI21_X4_LVT fr 715.0 15.5 15.5 0.0 8.2 0.8 3.0 1 129, 89
theDecoder/theALU/i_0_27/A->ZN
AOI221_X2_LVT rf 719.3 4.2 4.2 0.0 13.5 0.9 2.9 1 129, 89
theDecoder/theALU/i_0_26/B->ZN
AOI211_X2_LVT fr 771.5 52.2 52.2 0.0 5.3 0.8 4.6 1 129, 89
theDecoder/theALU/i_0_25/B2->ZN
OAI22_X2_LVT rf 781.1 9.7 9.7 0.0 31.8 0.8 2.7 1 129, 89
theDecoder/theALU/i_0_24/C2->ZN
AOI211_X2_LVT fr 815.5 34.4 34.4 0.0 4.0 0.9 3.1 1 129, 89
theDecoder/theALU/i_0_23/A->ZN
AOI221_X2_LVT rf 821.3 5.8 5.8 0.0 27.8 0.9 3.1 1 129, 89
theDecoder/theALU/i_0_22/A->ZN
AOI221_X2_LVT fr 874.9 53.7 53.7 0.0 5.4 0.9 3.1 1 129, 89
theDecoder/theALU/i_0_21/A->ZN
AOI221_X2_LVT rf 881.0 6.1 6.1 0.0 31.2 0.9 3.1 1 129, 89
theDecoder/theALU/i_0_20/C2->ZN
OAI222_X2_LVT fr 919.8 38.8 38.8 0.0 5.4 0.9 3.3 1 129, 89
theDecoder/theALU/i_0_19/A->ZN
OAI221_X2_LVT rf 936.3 16.6 16.6 0.0 29.2 0.9 4.7 1 129, 89
theDecoder/theALU/i_0_18/B2->ZN
AOI22_X4_LVT fr 966.6 30.3 30.3 0.0 8.6 0.8 4.4 1 129, 89
theDecoder/theALU/i_0_17/B2->ZN
OAI21_X4_LVT rf 973.1 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89
theDecoder/theALU/i_0_16/A->ZN
OAI21_X4_LVT fr 982.8 9.8 9.8 0.0 3.6 0.7 3.9 1 129, 89
theDecoder/theALU/i_0_13/B1->ZN
AOI21_X4_LVT rf 988.1 5.3 5.3 0.0 12.5 0.8 4.4 1 129, 89
theDecoder/theALU/i_0_12/A4->ZN
NOR4_X2_LVT fr 1044.5 56.5 56.5 0.0 2.9 0.8 2.8 1 129, 89
theDecoder/theALU/i_0_0/A3->ZN
OR3_X4_LVT rr 1062.9 18.3 18.3 0.0 29.1 0.7 18.9 2 129, 89
theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1069.5 6.7 6.7 0.0 9.3 0.7 4.3 1 129, 89
theDecoder/i_0_113/B1->ZN
AOI22_X4_LVT fr 1096.0 26.5 26.5 0.0 5.1 0.8 4.4 1 129, 89
theDecoder/i_0_111/A2->ZN
AOI22_X4_LVT rf 1102.4 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89
theDecoder/i_0_110/A2->ZN
NAND2_X4_LVT* fr 1121.6 19.2 19.2 0.0 4.4 9.0 37.6 13 129, 89
i_0_0_60/S->Z MUX2_X2_LVT* rf 1190.2 68.6 68.6 0.0 10.2 32.0 87.6 3 129, 89
led[7] f 1190.2 0.0 0.0 10.2 119, 257
--------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------
Tessent DFT complete
-------------------------------------
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