muellerlu fedfd92270 Initial commit

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constraints

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demo_chip_rtl

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docs

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libs

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oasys.tessent.00

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oasys.tessent.01

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oasys.tessent.02

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oasys.tessent.03

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output

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riscv_rtl

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scripts

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scripts_risc_v

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work

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.cleanup_lukas.sh.swp

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atpg.log

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cleanup.sh

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commands.txt

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cpu_patterns_serial.v

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cpu_patterns_serial.v.0.vec

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cpu_patterns_serial.v.cfg

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cpu_patterns_serial.v.info.dict

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cpu_patterns_serial.v.po.name

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cpu_patterns.stil

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oasys.cmd.00

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oasys.cmd.01

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oasys.cmd.02

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oasys.cmd.03

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oasys.log.00

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oasys.log.01

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oasys.log.02

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oasys.log.03

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Description

RiskV ASIC Projekt für BCDC

1 GiB

Languages

Verilog 51.4%

Coq 38.2%

Tcl 2.7%

SystemVerilog 2.5%

Assembly 1.7%

Other 3.3%