302 lines
20 KiB
Plaintext
302 lines
20 KiB
Plaintext
charapallivenkatsaja@efiapps0:/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock$ tessent -shell
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// Tessent Shell 2023.4-p1 Mon Feb 19 16:22:02 GMT 2024
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// Unpublished work. Copyright 2024 Siemens
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//
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// This material contains trade secrets or otherwise confidential
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// information owned by Siemens Industry Software Inc. or its affiliates
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// (collectively, "SISW"), or its licensors. Access to and use of this
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// information is strictly limited as set forth in the Customer's
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// applicable agreements with SISW.
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//
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// Siemens software executing under x86-64 Linux on Thu May 28 17:29:18 CEST 2026.
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// 64 bit version
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// Host: efiapps0.ads1.fh-nuernberg.de (12 x 3.5 GHz, 48014 MB RAM, 24575 MB Swap)
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//
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SETUP> source scri
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scripts scripts_risc_v
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SETUP> source scripts_risc_v/5_atpg.do
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// sub-command: set_context patterns -scan
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// sub-command: set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/tsdb_outdir
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// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib
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// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib
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// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib
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// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib
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// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib
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// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib
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// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib
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// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib
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// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib
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// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib
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// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib
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// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib
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// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib
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// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib
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// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib
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// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib
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// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib
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// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib
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// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/PLL.fslib
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// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/PLL.fslib
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// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/PLL.fslib
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// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/IO.fslib
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// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/IO.fslib
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// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/IO.fslib
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// sub-command: read_design cpu -design_id Scan_0
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// sub-command: add_black_boxes -modules " MemGen_16_10 "
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// Command 'add_black_boxes' requires an elaborated design. Automatically elaborating the design ...
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// Note: 36 duplicate cell library models were read. The last model read of the same name was kept.
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// To see detailed messages per duplicate model, issue 'set_cell_library_options -report_duplicate_models on'
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// before issuing 'read_cell_library'.
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// Warning: 1 cell library model contained 2 floating model outputs.
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// To see detailed messages per model, issue 'set_cell_library_options -report_floating_nets on'
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// before issuing 'read_cell_library'.
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// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
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// Model 'CLKGATE_X1_SVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib'
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// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
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// Model 'CLKGATE_X2_SVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib'
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// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
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// Model 'CLKGATE_X4_SVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib'
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// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
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// Model 'CLKGATE_X8_SVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib'
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// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
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// Model 'CLKGATE_X1' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib'
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// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
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// Model 'CLKGATE_X2' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib'
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// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
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// Model 'CLKGATE_X4' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib'
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// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
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// Model 'CLKGATE_X8' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib'
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// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
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// Model 'CLKGATE_X1_HVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib'
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// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
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// Model 'CLKGATE_X2_HVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib'
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// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
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// Model 'CLKGATE_X4_HVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib'
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// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
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// Model 'CLKGATE_X8_HVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib'
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// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
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// Model 'CLKGATE_X1_LVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib'
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// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
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// Model 'CLKGATE_X2_LVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib'
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// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
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// Model 'CLKGATE_X4_LVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib'
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// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in'
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// Model 'CLKGATE_X8_LVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib'
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// Note: Top design is 'cpu'.
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// Warning: 32 cases: Unused net in DFT library model
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// Warning: 106 cases: Undriven net in netlist module
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// Warning: 1 case: Floating input on instance in netlist
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// Warning: 47 cases: Net in netlist not connected
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// Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings
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// Design elaboration successful.
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// sub-command: add_black_boxes -modules " MemGen_32_11 "
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// sub-command: add_black_boxes -modules " main_mem "
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// sub-command: set_current_design cpu
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// Warning: Undefined modules were found.
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// Before using "set_system_mode" or "create_flat_model", you must either define
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// the missing modules using "read_verilog" and/or "read_cell_library", or use the
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// following command to treat them as black boxes:
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add_black_boxes -modules { \
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MemGen_16_10 \
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}
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// You can also use "add_black_boxes -auto" to black box all undefined modules but
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// it is recommended that you do not add this command to your dofile. Doing so may
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// unintentionally black-box new undefined modules in future runs.
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// Warning: 106 cases: Undriven net in netlist module
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// Warning: 1 case: Floating input on instance in netlist
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// Warning: 47 cases: Net in netlist not connected
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// Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings
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// Note: Design level set to 'physical_block' from previous settings
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// sub-command: set_design_level physical_block
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// sub-command: import_scan_mode unwrapped
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// Resetting design.
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// Warning: The current mode name was not specified and will be set to 'unwrapped'.
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// Different ATPG configurations should use different mode names, otherwise
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// they will overwrite each other in the TSDB when 'write_tsdb_data -replace' is called.
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// If you will have multiple ATPG configurations for this scan mode of this design,
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// use the 'set_current_mode' command to change the current mode name.
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// sub-command: set_system_mode analysis
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// Warning: Rule FN1 violation occurs 152 times
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// Flattening process completed, cell instances=4041, gates=16395, PIs=13, POs=12, CPU time=0.08 sec.
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// ---------------------------------------------------------------------------
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// Begin circuit learning analyses.
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// --------------------------------
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// Learning completed, CPU time=0.04 sec.
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// ---------------------------------------------------------------------------
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// Begin scan chain identification process, memory elements = 1059.
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// ---------------------------------------------------------------------------
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// Begin simulation of load_unload procedure.
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// Simulation of load_unload procedure completed, CPU time=0.0 sec.
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// Chain = unwrapped_chain1 successfully traced with scan_cells = 256.
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// Chain = unwrapped_chain2 successfully traced with scan_cells = 256.
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// Chain = unwrapped_chain3 successfully traced with scan_cells = 256.
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// Chain = unwrapped_chain4 successfully traced with scan_cells = 256.
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// 1024 scan cells have been identified in 4 scan chains.
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// Longest scan chain has 256 scan cells.
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// ---------------------------------------------------------------------------
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// Begin transparent latch checking for 35 latches.
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// ---------------------------------------------------------------------------
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// Number transparent latches = 35.
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// ---------------------------------------------------------------------------
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// Begin scan clock rules checking.
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// ---------------------------------------------------------------------------
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// 1 scan clock/set/reset lines have been identified.
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// All scan clocks successfully passed off-state check.
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// Capture clock is set to clk_25mhz.
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// ---------------------------------------------------------------------------
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// 35 non-scan memory elements are identified.
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// ---------------------------------------------------------------------------
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// 35 non-scan memory elements are identified as TLA. (D5)
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// ---------------------------------------------------------------------------
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// 64 gates may have an observable X-state. (E5)
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// sub-command: report_clocks
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User-defined Clock (1):
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=========================
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Sync and Async Source Clock
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============================
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----------- --------- --------
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Name Off State Internal
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----------- --------- --------
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'clk_25mhz' 0 No
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// sub-command: report_drc_rules
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D5: #fails=35 handling=warning (non-scan memory element)
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E5: #fails=64 handling=note (X-state propagation)
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// sub-command: set_fault_type stuck
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// sub-command: add_faults -all
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// sub-command: create_patterns
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// | ------------------------------------------------------------------------------------------------------------------ |
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// | Analyzing the design |
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// | |
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// | Current clock restriction setting: Domain_clock (edge interaction) |
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// | (optimal) |
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// | |
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// | Current abort limit setting: 30 |
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// | Calling: set_abort_limit 300 100 |
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// | ------------------------------------------------------------------------------------------------------------------ |
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// | |
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// | Current sequential depth: 0 (optimal) |
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// | |
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// | ------------------------------------------------------------------------------------------------------------------ |
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// ------------------------------------------------------------------------
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// Simulation performed for #gates = 16395 #faults = 4988
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// system mode = analysis pattern source = internal patterns
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// ------------------------------------------------------------------------
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// #patterns test #faults #faults # eff. # test process RE/AU/AAB
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// simulated coverage in list detected patterns patterns CPU time
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// --- ------ --- --- --- --- 6.31 sec 0/27368/0
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// 16 25.95% 0 2239 10 10 6.32 sec
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// -----------------------------------------------------------------------
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// Performing redundant fault identification for 27368 faults
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// -----------------------------------------------------------------------
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// deterministic ATPG invoked with abort limit = 300
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// # red. # non-red. # abort # remn. progress test process
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// faults faults faults faults coverage CPU time
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// 20 27338 10 0 100.00% 25.96% 1903.57 sec
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Statistics Report
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Stuck-at Faults
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---------------------------------------
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Fault Classes #faults
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(total)
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----------------------- --------------
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FU (full) 39020
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--------------------- --------------
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DS (det_simulation) 2239 ( 5.74%)
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DI (det_implication) 7351 (18.84%)
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UU (unused) 2062 ( 5.28%)
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RE (redundant) 20 ( 0.05%)
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AU (atpg_untestable) 27348 (70.09%)
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---------------------------------------
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Fault Sub-classes
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---------------------
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AU (atpg_untestable)
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BB (black_boxes) 24599 (63.04%)
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Unclassified 2749 ( 7.05%)
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---------------------------------------
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Coverage
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---------------------
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test_coverage 25.96%
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fault_coverage 24.58%
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atpg_effectiveness 100.00%
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---------------------------------------
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#test_patterns 10
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#simulated_patterns 16
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CPU_time (secs) 1925.7
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---------------------------------------
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// sub-command: report_statistics
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Statistics Report
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Stuck-at Faults
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---------------------------------------
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Fault Classes #faults
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(total)
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----------------------- --------------
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FU (full) 39020
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--------------------- --------------
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DS (det_simulation) 2239 ( 5.74%)
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DI (det_implication) 7351 (18.84%)
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UU (unused) 2062 ( 5.28%)
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RE (redundant) 20 ( 0.05%)
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AU (atpg_untestable) 27348 (70.09%)
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---------------------------------------
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Fault Sub-classes
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---------------------
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AU (atpg_untestable)
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BB (black_boxes) 24599 (63.04%)
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Unclassified 2749 ( 7.05%)
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---------------------------------------
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Coverage
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---------------------
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test_coverage 25.96%
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fault_coverage 24.58%
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atpg_effectiveness 100.00%
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---------------------------------------
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#test_patterns 10
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#simulated_patterns 16
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CPU_time (secs) 1925.7
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---------------------------------------
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// sub-command: report_faults -summary
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Statistics Report
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Stuck-at Faults
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---------------------------------------
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Fault Classes #faults
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(total)
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----------------------- --------------
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FU (full) 39020
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--------------------- --------------
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DS (det_simulation) 2239 ( 5.74%)
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DI (det_implication) 7351 (18.84%)
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UU (unused) 2062 ( 5.28%)
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RE (redundant) 20 ( 0.05%)
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AU (atpg_untestable) 27348 (70.09%)
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---------------------------------------
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Fault Sub-classes
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---------------------
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AU (atpg_untestable)
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BB (black_boxes) 24599 (63.04%)
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Unclassified 2749 ( 7.05%)
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---------------------------------------
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Coverage
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---------------------
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test_coverage 25.96%
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fault_coverage 24.58%
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atpg_effectiveness 100.00%
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---------------------------------------
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#test_patterns 10
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#simulated_patterns 16
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CPU_time (secs) 1925.7
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---------------------------------------
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// sub-command: write_patterns cpu_patterns.stil -stil -replace
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// sub-command: write_patterns cpu_patterns_serial.v -verilog -serial -replace
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// sub-command: write_tsdb_data -replace
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// Writing ./oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped.tcd.gz
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// Writing ./oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped.flat.gz
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// Writing ./oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped_stuck.patdb
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// Writing ./oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped_stuck.faults.gz
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// sub-command: exit
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