43 lines
1.7 KiB
Plaintext
43 lines
1.7 KiB
Plaintext
set_context patterns -scan
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set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/tsdb_outdir
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read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib
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read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib
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read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib
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read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib
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read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib
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read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib
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read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/PLL.fslib
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read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/IO.fslib
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read_design cpu -design_id Scan_0
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add_black_boxes -modules { MemGen_16_10 }
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add_black_boxes -modules { MemGen_32_11 }
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add_black_boxes -modules { main_mem }
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set_current_design cpu
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set_design_level physical_block
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# import_scan_mode reads the TCD which now includes clk12p5_reg/Q as TestClock
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import_scan_mode unwrapped
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set_system_mode analysis
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report_clocks
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report_drc_rules
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set_fault_type stuck
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add_faults -all
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create_patterns
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report_statistics
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report_faults -summary
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write_patterns cpu_patterns.stil -stil -replace
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write_patterns cpu_patterns_serial.v -verilog -serial -replace
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write_tsdb_data -replace
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exit
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