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BCDC_RISKV
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11a19934be9e741aff93d16a28a9d198510bcc15
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muellerlu
11a19934be
Lösung für Scan insertion und ATPG
2026-06-16 11:13:19 +02:00
constraints
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
docs
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
Documents
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
libs
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
RISC-V_no_Macros_2_clk_atpg_done
Lösung für Scan insertion und ATPG
2026-06-16 11:13:19 +02:00
riscv_rtl
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
scripts_risc_v
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
scripts_risc_v_solution
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
.cleanup_lukas.sh.swp
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
cleanup.sh
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
commands_help.txt
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
RISC-V_no_Macros_2_clk_atpg_done (Kopie).zip
Add lab zip files for synthesis
2026-06-16 09:03:34 +02:00
RISC-V_no_Macros_2_clk_atpg_done (Lösung).zip
Lösung für Scan insertion und ATPG
2026-06-16 11:13:19 +02:00
riscv_2clk_mbist_simulation_lab1.zip
Add lab zip files
2026-06-15 15:31:14 +02:00
S
Description
RiskV ASIC Projekt für BCDC
1
GiB
Languages
Verilog
51.4%
Coq
38.2%
Tcl
2.7%
SystemVerilog
2.5%
Assembly
1.7%
Other
3.3%
