39 lines
1004 B
Tcl
Executable File
39 lines
1004 B
Tcl
Executable File
#########################################################
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# dse_base.tcl
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#
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# Description: Sets up the design for exploration
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#
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# Usage: source in Oasys-RTL Command prompt
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#
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# Dependencies: init_design.tcl
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#########################################################
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#Initialize script parameters
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source scripts/init_design.tcl
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#Disable warning messages
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message -enable false TA-116
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message -enable false LIB-136
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message -enable false LIB-114
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message -enable false NL-138
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message -enable false NL-120
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source scripts/open_database.tcl
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###########################
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# If available, synthesize opencore files
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# instead of the pre-optimized ODB file
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############################
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# read_verilog $rtl_list -include $search_path
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# synthesize -module ${top_module} -map_to_scan -gate_clock
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# create_clock -period 2.50ns -name sysclk sysclk
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# read_sdc -verbose $demo_chip_sdc_files
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#insert clk explorer here
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#Optimize
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optimize -virtual
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report_clocks
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report_power
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report_design_metrics
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