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BCDC_RISKV
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muellerlu
5abe57b7eb
Add lab zip files for synthesis
2026-06-16 09:03:34 +02:00
constraints
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
docs
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2026-06-09 08:33:18 +02:00
Documents
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2026-06-09 08:33:18 +02:00
libs
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2026-06-09 08:33:18 +02:00
riscv_rtl
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2026-06-09 08:33:18 +02:00
scripts_risc_v
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2026-06-09 08:33:18 +02:00
scripts_risc_v_solution
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2026-06-09 08:33:18 +02:00
.cleanup_lukas.sh.swp
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2026-06-09 08:33:18 +02:00
cleanup.sh
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2026-06-09 08:33:18 +02:00
commands_help.txt
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RISC-V_no_Macros_2_clk_atpg_done (Kopie).zip
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2026-06-16 09:03:34 +02:00
riscv_2clk_mbist_atpg_done_lab_2 (excersie).zip
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2026-06-15 15:31:14 +02:00
riscv_2clk_mbist_simulation_lab1.zip
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2026-06-15 15:31:14 +02:00
S
Description
RiskV ASIC Projekt für BCDC
1
GiB
Languages
Verilog
51.4%
Coq
38.2%
Tcl
2.7%
SystemVerilog
2.5%
Assembly
1.7%
Other
3.3%
