muellerlu 5abe57b7eb Add lab zip files for synthesis

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constraints

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docs

RISC_V_LAB hinzugefügt

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Documents

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libs

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riscv_rtl

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scripts_risc_v

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scripts_risc_v_solution

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.cleanup_lukas.sh.swp

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cleanup.sh

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commands_help.txt

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RISC-V_no_Macros_2_clk_atpg_done (Kopie).zip

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riscv_2clk_mbist_atpg_done_lab_2 (excersie).zip

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riscv_2clk_mbist_simulation_lab1.zip

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S

Description

RiskV ASIC Projekt für BCDC

1 GiB

0 Stars 1 Watchers 0 Forks

Languages

Verilog 51.4%

Coq 38.2%

Tcl 2.7%

SystemVerilog 2.5%

Assembly 1.7%

Other 3.3%