26 lines
751 B
Systemverilog
26 lines
751 B
Systemverilog
// MemGen_16_10_stub.sv
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// Behavioral stub - ports matched from MemGen_32_11.sv instantiation
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module MemGen_16_10 #(
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parameter ADDR_WIDTH = 10,
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parameter DATA_WIDTH = 16
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)(
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input logic chip_en,
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input logic clock,
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input logic [ADDR_WIDTH-1:0] addr,
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input logic rd_en,
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output logic [DATA_WIDTH-1:0] rd_data,
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input logic wr_en,
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input logic [DATA_WIDTH-1:0] wr_data
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);
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logic [DATA_WIDTH-1:0] mem [0:(2**ADDR_WIDTH)-1];
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always_ff @(posedge clock) begin
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if (chip_en) begin
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if (wr_en)
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mem[addr] <= wr_data;
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else if (rd_en)
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rd_data <= mem[addr];
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end
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end
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endmodule
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