85 lines
2.8 KiB
Bash
Executable File
85 lines
2.8 KiB
Bash
Executable File
#! /bin/sh -f
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#\
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exec tessent -shell -log logfiles/$0.log -replace -dofile "$0"
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# Set the context to insert DFT into RTL-level design
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set_context dft -rtl -design_id rtl1
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# Set the location of the TSDB. Default is the current working directory.
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set_tsdb_output_directory ../tsdb_outdir
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# Read the verilog
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read_verilog ../RTL/cpu_top.v
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read_verilog ../RTL/piccpu.v
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# Read the cell library
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read_cell_library ../library/standard_cells/tessent/adk.tcelllib
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read_cell_library ../library/memories/picdram.tcelllib
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# Define location of memory library files
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set_design_sources -format tcd_memory -Y ../library/memories -extension tcd_memory
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set_current_design cpu_top
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# Set the design level before running check_design_rules
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set_design_level chip
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# Define set_dft_specification_requirements
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set_dft_specification_requirements -boundary_scan on -memory_test on
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# Specify the TAP pins using set_attribute_value
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set_attribute_value tck_p -name function -value tck
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set_attribute_value tdi_p -name function -value tdi
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set_attribute_value tms_p -name function -value tms
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set_attribute_value trst_p -name function -value trst
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set_attribute_value tdo_p -name function -value tdo
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set_boundary_scan_port_options clk* -cell_options dont_touch
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set_boundary_scan_port_options ramclk_p -cell_options dont_touch
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# Specify the clocks feeding memories
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add_clocks 0 ramclk_p -period 5ns
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check_design_rules
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# Create and report a DFT Specification
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set spec [create_dft_specification]
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report_config_data $spec
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# Set parameter to divide the boundary scan chain into smaller segments to be used during logic test
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set_config_value $spec/BoundaryScan/max_segment_length_for_logictest 65
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report_config_data $spec
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# Add auxilary mux on the inputs and outputs used for EDT Channel pins
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read_config_data -in ${spec}/BoundaryScan -from_string {
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AuxiliaryInputOutputPorts {
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auxiliary_input_ports : portain_p[0], portain_p[1], portain_p[2], enable_p, pdata_p[0], pdata_p[1] ;
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auxiliary_output_ports : portbout_p[0], portbout_p[1], portbout_p[2] ;
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}
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}
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report_config_data $spec
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# Generate and insert the hardware
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process_dft_specification
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# Extract IJAG network and create ICL file for the design
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extract_icl
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# Provides new and original updated RTL into this new file to be elaborated and Synthesized later
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# If not using logic test (EDT insertion in next step) this would be used for synthesis
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#write_design_import_script use_in_synthesis.tcl -replace
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# Generate patterns to verify the inserted DFT logic
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create_pattern_specification
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process_patterns_specification
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# Point to the libraries and run the simulation
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set_simulation_library_sources -v ../library/standard_cells/verilog/adk.v -v ../library/memories/picdram.v
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run_testbench_simulations
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# If simulation fails, use this command to see which pattern failed
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#check_testbench_simulations
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exit
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