This website requires JavaScript.
Explore
Help
Sign In
kuntzschcl
/
BCDC_RISKV
Watch
1
Star
0
Fork
0
Code
Issues
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
5
Commits
2
Branches
0
Tags
973d18f2cd64a12650686ff04561f6fc586d7dfe
T
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
muellerlu
973d18f2cd
Lösung für Scan insertion und ATPG
2026-06-16 11:13:19 +02:00
constraints
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
docs
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
Documents
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
libs
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
RISC-V_no_Macros_2_clk_atpg_done
Lösung für Scan insertion und ATPG
2026-06-16 11:13:19 +02:00
riscv_rtl
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
scripts_risc_v
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
scripts_risc_v_solution
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
.cleanup_lukas.sh.swp
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
cleanup.sh
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
commands_help.txt
RISC_V_LAB hinzugefügt
2026-06-09 08:33:18 +02:00
RISC-V_no_Macros_2_clk_atpg_done (Kopie).zip
Add lab zip files for synthesis
2026-06-16 09:03:34 +02:00
riscv_2clk_mbist_simulation_lab1.zip
Add lab zip files
2026-06-15 15:31:14 +02:00
S
Description
RiskV ASIC Projekt für BCDC
1
GiB
Languages
Verilog
51.4%
Coq
38.2%
Tcl
2.7%
SystemVerilog
2.5%
Assembly
1.7%
Other
3.3%
