33 lines
1005 B
Tcl
Executable File
33 lines
1005 B
Tcl
Executable File
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#########################################################
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# 3_export_design.tcl
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#
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# Description: Export the design data
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#
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# Usage: source in Oasys-RTL Command prompt
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#
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# Dependencies: init_design.tcl
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# 1_load_design.tcl
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# 2_synthesize_optimize.tcl
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# Launched from Oasys-RTL shell after
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# synthesis and optimization
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#
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#########################################################
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#Check if dependent scripts have been loaded
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if {![info exists top_module]} {
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source scripts/init_design.tcl
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}
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# Write results
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write_db ${output_dir}/odb/demo_chip.oasys_final.odb
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write_verilog ${output_dir}/demo_chip.oasys_final.v
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write_sdc ${output_dir}/demo_chip.oasys_final.sdc
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write_def ${output_dir}/demo_chip.def
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write_stil ${output_dir}/demo_chip.stil
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write_ctl ${output_dir}/demo_chip.ctl
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echo "\n-----------------------------"
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echo "\nDesign data exported to output dir."
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echo "\n-----------------------------\n"
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