muellerlu fedfd92270 Initial commit

2026-05-29 10:19:13 +02:00

constraints

Initial commit

2026-05-29 10:19:13 +02:00

demo_chip_rtl

Initial commit

2026-05-29 10:19:13 +02:00

docs

Initial commit

2026-05-29 10:19:13 +02:00

libs

Initial commit

2026-05-29 10:19:13 +02:00

oasys.tessent.00

Initial commit

2026-05-29 10:19:13 +02:00

oasys.tessent.01

Initial commit

2026-05-29 10:19:13 +02:00

oasys.tessent.02

Initial commit

2026-05-29 10:19:13 +02:00

oasys.tessent.03

Initial commit

2026-05-29 10:19:13 +02:00

output

Initial commit

2026-05-29 10:19:13 +02:00

riscv_rtl

Initial commit

2026-05-29 10:19:13 +02:00

scripts

Initial commit

2026-05-29 10:19:13 +02:00

scripts_risc_v

Initial commit

2026-05-29 10:19:13 +02:00

work

Initial commit

2026-05-29 10:19:13 +02:00

.cleanup_lukas.sh.swp

Initial commit

2026-05-29 10:19:13 +02:00

atpg.log

Initial commit

2026-05-29 10:19:13 +02:00

cleanup.sh

Initial commit

2026-05-29 10:19:13 +02:00

commands.txt

Initial commit

2026-05-29 10:19:13 +02:00

cpu_patterns_serial.v

Initial commit

2026-05-29 10:19:13 +02:00

cpu_patterns_serial.v.0.vec

Initial commit

2026-05-29 10:19:13 +02:00

cpu_patterns_serial.v.cfg

Initial commit

2026-05-29 10:19:13 +02:00

cpu_patterns_serial.v.info.dict

Initial commit

2026-05-29 10:19:13 +02:00

cpu_patterns_serial.v.po.name

Initial commit

2026-05-29 10:19:13 +02:00

cpu_patterns.stil

Initial commit

2026-05-29 10:19:13 +02:00

oasys.cmd.00

Initial commit

2026-05-29 10:19:13 +02:00

oasys.cmd.01

Initial commit

2026-05-29 10:19:13 +02:00

oasys.cmd.02

Initial commit

2026-05-29 10:19:13 +02:00

oasys.cmd.03

Initial commit

2026-05-29 10:19:13 +02:00

oasys.log.00

Initial commit

2026-05-29 10:19:13 +02:00

oasys.log.01

Initial commit

2026-05-29 10:19:13 +02:00

oasys.log.02

Initial commit

2026-05-29 10:19:13 +02:00

oasys.log.03

Initial commit

2026-05-29 10:19:13 +02:00

S

Description

RiskV ASIC Projekt für BCDC

1 GiB

0 Stars 1 Watchers 0 Forks

Languages

Verilog 51.4%

Coq 38.2%

Tcl 2.7%

SystemVerilog 2.5%

Assembly 1.7%

Other 3.3%