66 lines
4.4 KiB
ArmAsm
66 lines
4.4 KiB
ArmAsm
// *********************************************************************************************
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// Description : Assembly instructions for decoder test
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 15.Oct.2025 by Hussein Elzomor
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// Last Modified : 15.Oct.2025 by Hussein Elzomor
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// -----
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// HISTORY : Date By Comments
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// ----------- --------- -------------------------------------------------
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// *********************************************************************************************
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# Iteration over all implemented instructions to test decoder
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# R-instruction # Hex # bin f7 rs2 rs1 f3 rd opcode
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add x1 , x1 , x1 # 0x001080B3 # 0b 0000000 00001 00001 000 00001 0110011
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sub x2 , x2 , x2 # 0x40210133 # 0b 0100000 00010 00010 000 00010 0110011
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xor x3 , x3 , x3 # 0x0031C1B3 # 0b 0000000 00011 00011 100 00011 0110011
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or x4 , x4 , x4 # 0x00426233 # 0b 0000000 00100 00100 110 00100 0110011
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and x5 , x5 , x5 # 0x0052F2B3 # 0b 0000000 00101 00101 111 00101 0110011
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sll x6 , x6 , x6 # 0x00631333 # 0b 0000000 00110 00110 001 00110 0110011
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srl x7 , x7 , x7 # 0x0073D3B3 # 0b 0000000 00111 00111 101 00111 0110011
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sra x8 , x8 , x8 # 0x40845433 # 0b 0100000 01000 01000 101 01000 0110011
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slt x9 , x9 , x9 # 0x0094A4B3 # 0b 0000000 01001 01001 010 01001 0110011
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sltu x10, x10, x10 # 0x00A53533 # 0b 0000000 01010 01010 011 01010 0110011
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# I-instruction # Hex # bin imm rs1 f3 rd opcode
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addi x11, x11, 11 # 0x00B58593 # 0b 000000001011 01011 000 01011 0010011
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xori x12, x12, 12 # 0x00C64613 # 0b 000000001100 01100 100 01100 0010011
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ori x13, x13, 13 # 0x00D6E693 # 0b 000000001101 01101 110 01101 0010011
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andi x14, x14, 14 # 0x00E77713 # 0b 000000001110 01110 111 01110 0010011
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slli x15, x15, 15 # 0x00F79793 # 0b 000000001111 01111 001 01111 0010011
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srli x16, x16, 16 # 0x01085813 # 0b 000000010000 10000 101 10000 0010011
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srai x17, x17, 17 # 0x4118D893 # 0b 010000010001 10001 101 10001 0010011
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slti x18, x18, 18 # 0x01292913 # 0b 000000010010 10010 010 10010 0010011
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sltiu x19, x19, 19 # 0x0139B993 # 0b 000000010011 10011 011 10011 0010011
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lb x20, 20(x20) # 0x014A0A03 # 0b 000000010100 10100 000 10100 0000011
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lh x21, 21(x21) # 0x015A9A83 # 0b 000000010101 10101 001 10101 0000011
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lw x22, 22(x22) # 0x016B2B03 # 0b 000000010110 10110 010 10110 0000011
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lbu x23, 23(x23) # 0x017BCB83 # 0b 000000010111 10111 100 10111 0000011
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lhu x24, 24(x24) # 0x018C5C03 # 0b 000000011000 11000 101 11000 0000011
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# S-instruction # Hex # bin imm rs2 rs1 f3 imm opcode
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sb x25, 25(x25) # 0x019C8CA3 # 0b 0000000 11001 11001 000 11001 0100011
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sh x26, 26(x26) # 0x01AD1D23 # 0b 0000000 11010 11010 001 11010 0100011
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sw x27, 27(x27) # 0x01BDADA3 # 0b 0000000 11011 11011 010 11011 0100011
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# B-instruction # Hex # bin imm rs2 rs1 f3 imm opcode
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beq x28, x28, 28 # 0x01CE0E63 # 0b 0000000 11100 11100 000 11100 1100011
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bne x28, x28, 28 # 0x01CE1E63 # 0b 0000000 11100 11100 001 11100 1100011
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blt x30, x30, 30 # 0x01EF4F63 # 0b 0000000 11110 11110 100 11110 1100011
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bge x30, x30, 30 # 0x01EF5F63 # 0b 0000000 11110 11110 101 11110 1100011
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bltu x2 , x2 , 2 # 0x00216163 # 0b 0000000 00010 00010 110 00010 1100011
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bgeu x2 , x2 , 2 # 0x00217163 # 0b 0000000 00010 00010 111 00010 1100011
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# J-instruction # Hex # bin f7 rd opcode
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jal x4 , 4 # 0x0040026F # 0b 00000000010000000000 00100 1101111
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jalr x4 , x4, 4 # 0x00420267 # 0b 00000000010000100000 00100 1100111
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# U-instruction # Hex # bin f7 rd opcode
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lui x5 , 5 # 0x000052B7 # 0b 00000000000000000101 00101 0110111
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auipc x6 , 6 # 0x00006317 # 0b 00000000000000000110 00110 0010111
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