BCDC_RISKV/scripts_risc_v/oasys_tessent_dft.tcl

if {[info exists tessent_build] && [string match $dft_flow tessent]} {
  puts "INFO::using $tessent_build build to run the Tessent DFT flow"
} else {
  puts "ERROR::To run the tessent DFT flow, Please set the following variables (as shown in the scripts/init_design.tcl file)"
  puts "    - 'tessent_build' variable to the tessent executable"
  puts "    # set dft_flow tessent"
  puts ""
  puts "    - 'dft_flow' variable to 'tessent'"
  puts "    # set tessent_build \$env(TESSENT)/bin/tessent"
  return 0 
}

config_tessent -exec_path $tessent_build


#=======================================================#
#Define dft settings
#=======================================================#

define_test_clock -pin clk_25mhz

#define_test_pin -pin reset -scan 1 
# Define scan enable port (create it since counter doesn't have one)
#define_test_pin -pin scan_en -scan 1 -default_scan_enable -create_port
define_test_pin -pin scan_en -scan_mode 1 -default_scan_enable -create_port

# Add this - exclude main_mem from scan insertion entirely
# Exclude memory subsystem from scan insertion
set_dont_scan theMem true          

# Define reset as test pin
#define_test_pin -pin btn[0] reset -scan 1
#For reset: check the polarity:
#Active-high reset → -scan_mode 0-> so it does no reset during scan
#Active-low reset → -scan_mode 1
define_test_pin -name reset -pin btn[0] -scan_mode 1


# connect_clock_gating_test_pin -test_pin scan_mode_pad/C

#set_dont_scan clk12p5_reg true

#config_tessent_scan -add_dofile_cmds "add_input_constraints scan_en -C1"

# Check the DFT violation and use autofix feature to adress them
check_dft -auto_test_clock -auto_test_pins

#=======================================================#
# Pre fix_dft_violation database
#=======================================================#
write_db  ${output_dir}/odb/riscv.tessent_pre_fix.odb
fix_dft_violations -type all -test_clock clk_25mhz -test_control scan_en

#fix_dft_violations -type all -test_clock sysclk_byp -test_control scan_mode_pad/C

#check_dft < Error: There was 1 S6 violation (driven scan-in pin of a sub chain or of a scan cell in unspecified scncan)
#//For failed scan cells, use "add_scan_chains" or "add_scan_segments" commands to declare previously inserted scan chains.

report_dft_violations

#=======================================================#
#Final optimize
#=======================================================#
optimize 
write_db      ${output_dir}/odb/riscv.tessent_post_fix.odb
write_verilog ${output_dir}/riscv.tessent_post_fix.v
#report_timing
#report_endpoints
#report_power
#report_path_groups

#========================================================#
# Formalpro verification command
#========================================================#

#verify ${output_dir}/verilog/post_optimize.v -base_directory post_optimize


#=======================================================#
# configuring Tessent build
#=======================================================#
#Specify the path to Tessent exec.

#config_tessent -exec_path $tessent_build

#=======================================================#
# Tessent TPI
#=======================================================#

#set fastscan_path "${ekit_dir}/libs/fastscan"
#config_tessent -ignore_clock_gating "on"
#set lib_list [glob -nocomplain $fastscan_path/*.fslib ]
#config_tessent -library $lib_list
#config_tessent_tpi  -total_number 2% -control_point_enable control_test_point_en -observe_point_enable observe_test_point_en

#run_tessent_tpi

# Only add library if it exists
set fastscan_path "${ekit_dir}/libs/fastscan"
if {[file exists $fastscan_path]} {
  set lib_list [glob -nocomplain $fastscan_path/*.fslib]
  if {[llength $lib_list] > 0} {
    config_tessent -library $lib_list
  }
}

#=======================================================#
# WICHTIG: clk12p5_reg von Scan ausschließen
# Dieser interne Clock-Teiler-FF verursacht den S6-Fehler,
# weil fix_dft_violations bereits einen MUX-SI daran
# verdrahtet hat, den Tessent als "undeklarierte Sub-Chain"
# erkennt.
#=======================================================#
#set_dont_scan clk12p5_reg
#add_scan_segments clk12p5_reg

# Skip TPI for counter - coverage already high
# run_tessent_tpi  ← not needed

#========================================================#
# Formalpro verification command
#========================================================#

#verify ${output_dir}/verilog/post_tpi.v -base_directory post_tpi


#=======================================================#
# Tessent SCAN only
#=======================================================#

echo "\n--------------check dft---------------"
check_dft

echo "\n--------------define Scan-Chains---------------"
# Scan-Chains definieren
for {set i 1} {$i <= 4} {incr i} {
    define_scan_chain -scan_in SI_$i -scan_out SO_$i  -create_port
}

#define_scan_chain -scan_in SI_1 -scan_out SO_1 -create_port
echo "\n----------run_tessent_scan----------------"
run_tessent_scan

write_db      ${output_dir}/odb/riscv.tessent_post_scan.odb
write_verilog ${output_dir}/riscv.tessent_post_scan.v

echo "\n----------report_power----------------"
report_power
echo "\n----------report_path_groups----------------"
report_path_groups
echo "\n----------report_scan_chains----------------"
report_scan_chains
echo "\n----------report_timing----------------"
report_timing

#========================================================#
#Formalpro verification command
#========================================================#

#verify ${output_dir}/verilog/post_dft.v -base_directory post_dft