88 lines
2.9 KiB
Plaintext
88 lines
2.9 KiB
Plaintext
#########################################################
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# 4_mbist_tessent_shell.tcl
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#
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# Description: MemoryBIST insertion für RISC-V Design
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#
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# Usage: Im Tessent Shell Prompt:
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# SETUP> set script_dir "scripts_risc_v"
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# SETUP> set ekit_dir "."
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# SETUP> source scripts_risc_v/4_mbist_tessent_shell.tcl
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#
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# Dependencies: - nangate_complete.tcelllib (aus gen_tcelllib.tcl)
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# - riscv.tessent_post_scan.v (aus Oasys DFT Flow)
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# - MemGen_16_10.memlib
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#########################################################
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set script_dir "scripts_risc_v"
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if {![info exists ekit_dir]} {
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set ekit_dir [file dirname ${script_dir}]
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}
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#----------------------------------------------------------
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# 1. Kontext setzen - Gate-Level Netlist
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#----------------------------------------------------------
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set_context dft -no_rtl
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#----------------------------------------------------------
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# 2. Libraries laden
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#----------------------------------------------------------
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# Tessent Cell Library
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read_cell_library ${ekit_dir}/output/nangate_complete.tcelllib
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# Memory BIST Model für MemGen_16_10
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read_core_descriptions ${ekit_dir}/libs/MemGen_16_10.memlib
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#----------------------------------------------------------
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# 3. Gate-Level Netlist laden
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#----------------------------------------------------------
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read_verilog ${ekit_dir}/output/riscv.tessent_post_scan.v
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#----------------------------------------------------------
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# 4. Top-Level und Design-Level setzen
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#----------------------------------------------------------
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set_current_design cpu
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set_design_level chip
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#----------------------------------------------------------
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# 5. MBIST Anforderungen setzen
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#----------------------------------------------------------
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set_dft_specification_requirements -memory_test on
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# Gefundene Memory-Instanzen anzeigen
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report_memory_instances
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#----------------------------------------------------------
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# 6. Clocks definieren
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#----------------------------------------------------------
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add_clocks clk_25mhz -period 40ns -label mbist_clk
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#----------------------------------------------------------
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# 7. Design Rule Check
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#----------------------------------------------------------
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check_design_rules
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#----------------------------------------------------------
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# 8. DFT Specification erstellen und verarbeiten
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#----------------------------------------------------------
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set dft_spec [create_dft_specification]
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report_config_data $dft_spec
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validate_dft_specification
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process_dft_specification
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extract_icl
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#----------------------------------------------------------
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# 9. Pattern Generation
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#----------------------------------------------------------
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set pat_spec [create_patterns_specification]
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process_patterns_specification
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#----------------------------------------------------------
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# 10. Simulation und Synthese
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#----------------------------------------------------------
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run_testbench_simulations
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check_testbench_simulations
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run_synthesis
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exit
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