ESY1_Projekt_2022/Bus_if/Bus_if.sv

interface Bus_if (input clk);
    logic sbclk;
    logic sbstb;
    logic sbrw;
    logic[7:0] sbadr;
    logic[7:0] sbdat_r;
    logic[7:0] sbdat_w;
    logic sback;
    logic[9:0] Data;
    logic SendData;
    logic TimerMeas;
    logic DataValid;
    logic AlarmAmpel;
    logic TasteAktiv;
    logic Alarm_R;
    logic TimerEN;
    logic Taste;
    logic ReadTemp;
    logic LEDg;
    logic LEDr;

    modport Fsm (
        input clk,
        input AlarmAmpel,
        input DataValid,
        input TasteAktiv,
        output Alarm_R,
        output SendData,
        output TimerEN
    );

    modport timer (
        input clk,
        input Taste,
        input TimerEN,
        output ReadTemp,
        output TasteAktiv
    );

/*
    module parallelport wird in top level design
    ohne modport verbunden, da inEndOfConv nicht
    Teil des Bus_if ist.
*/
endinterface //Bus