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ESY1_Projekt_2022
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Added modport in Bus_if for Fsm
top_level_design
sessleral71711
2 years ago
parent
19177edb3f
commit
613bffbcfc
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Bus_if/Bus_if.sv
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Bus_if/Bus_if.sv
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@@ -19,4 +19,14 @@ interface Bus_if (input clk);
logic ReadTemp;
logic LEDg;
logic LEDr;
modport Fsm (
input clk,
input AlarmAmpel,
input DataValid,
input TasteAktiv,
output Alarm_R,
output SendData,
output TimerEN
);
endinterface //Bus
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