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Added parallelport, timer and ampelsteuerung

top_level_design
sessleral71711 1 year ago
parent
commit
026899b930
2 changed files with 36 additions and 4 deletions
  1. 2
    3
      Source_Ampel/rgb_led_top.sv
  2. 34
    1
      Top/Top.sv

+ 2
- 3
Source_Ampel/rgb_led_top.sv View File

@@ -3,8 +3,6 @@ input wire clk12M,
input wire rst,
input wire [7:0] data_input,
input wire data_valid,
output reg REDn,
output reg GRNn,
output reg RED,
output reg GRN,
output reg alarm
@@ -12,7 +10,8 @@ output reg alarm
wire red_pwm;
wire grn_pwm;
reg REDn;
reg GRNn;
defparam U1.on_hi = 2'b10;
defparam U1.on_lo = 2'b01;
defparam U1.off = 2'b00;

+ 34
- 1
Top/Top.sv View File

@@ -1,13 +1,20 @@
`include "../spi_interface.v"
`include "../fsm/Fsm.sv"
`include "../Bus_if/Bus_if.sv"
`include "../timer_port/timer_top.sv"

module Top(
input wire clk
input wire clk,
input wire rst,
input wire endOfConv,
output wire LEDg,
output wire LEDr,
output wire AlarmAmpel
);
// Bus (Interface)
Bus_if bus(.clk(clk));
// SPI Interface
// FSM
Fsm fsm(
.clk(clk),
@@ -19,8 +26,34 @@ module Top(
.outTimerEN(bus.TimerEN)
);
// Parallelport
parallelport parallelport1 (
.inClk(clk),
.inTimerMeas(bus.TimerMeas),
.inEndOfConv(endOfConv),
.inData(bus.Data),
.outDataValid(bus.DataValid),
.outData(bus.Data)
);
// FRAM-Controller
// Timer
timer timer1 (
.inClk(clk),
.inTaste(bus.Taste),
.inEN(bus.TimerEN),
.outReadTemp(bus.ReadTemp),
.outTasteAktiv(bus.TasteAktiv)
);
// Ampelsteuerung
led_top ampelsteuerung (
.clk12M(clk),
.rst(rst),
.data_input(bus.Data),
.data_valid(bus.DataValid),
.RED(LEDr),
.GRN(LEDg),
.alarm(bus.AlarmAmpel)
);

assign AlarmAmpel = bus.AlarmAmpel;
endmodule

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