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Added SPI interface to top level design

main
sessleral71711 1 year ago
parent
commit
15b48049ab
1 changed files with 15 additions and 3 deletions
  1. 15
    3
      Top/Top.sv

+ 15
- 3
Top/Top.sv View File

@@ -1,7 +1,7 @@
`include "../spi_interface.v"
`include "../fsm/Fsm.sv"
`include "../Bus_if/Bus_if.sv"
`include "../timer_port/timer_top.sv"
`include "../spi_interface_radiant/spi_interface.sv"

module Top(
input wire clk,
@@ -9,11 +9,14 @@ module Top(
input wire endOfConv,
output wire LEDg,
output wire LEDr,
output wire AlarmAmpel
output wire AlarmAmpel,
output wire Alarm_R
);
// Bus (Interface)
Bus_if bus(.clk(clk));
// SPI Interface
spi_interface_ports spi_bus(.clk(clk));

// FSM
Fsm fsm(
.clk(clk),
@@ -53,5 +56,14 @@ module Top(
.alarm(bus.AlarmAmpel)
);

assign AlarmAmpel = bus.AlarmAmpel;
assign AlarmAmpel = bus.AlarmAmpel;
assign Alarm_R = bus.Alarm_R;

assign bus.sbclk = spi_bus.sb_clk_i;
assign bus.sbstb = spi_bus.sb_stb_i;
assign bus.sbrw = spi_bus.sb_wr_i;
assign bus.sbadr = spi_bus.sb_adr_i;
assign bus.sbdat_r = spi_bus.sb_dat_i;
assign bus.sbdat_w = spi_bus.sb_dat_o;
assign bus.sback = spi_bus.sb_ack_o;
endmodule

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