Added SPI interface to top level design
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18
Top/Top.sv
18
Top/Top.sv
@ -1,7 +1,7 @@
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`include "../spi_interface.v"
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`include "../fsm/Fsm.sv"
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`include "../Bus_if/Bus_if.sv"
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`include "../timer_port/timer_top.sv"
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`include "../spi_interface_radiant/spi_interface.sv"
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module Top(
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input wire clk,
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@ -9,11 +9,14 @@ module Top(
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input wire endOfConv,
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output wire LEDg,
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output wire LEDr,
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output wire AlarmAmpel
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output wire AlarmAmpel,
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output wire Alarm_R
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);
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// Bus (Interface)
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Bus_if bus(.clk(clk));
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// SPI Interface
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spi_interface_ports spi_bus(.clk(clk));
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// FSM
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Fsm fsm(
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.clk(clk),
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@ -53,5 +56,14 @@ module Top(
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.alarm(bus.AlarmAmpel)
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);
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assign AlarmAmpel = bus.AlarmAmpel;
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assign AlarmAmpel = bus.AlarmAmpel;
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assign Alarm_R = bus.Alarm_R;
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assign bus.sbclk = spi_bus.sb_clk_i;
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assign bus.sbstb = spi_bus.sb_stb_i;
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assign bus.sbrw = spi_bus.sb_wr_i;
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assign bus.sbadr = spi_bus.sb_adr_i;
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assign bus.sbdat_r = spi_bus.sb_dat_i;
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assign bus.sbdat_w = spi_bus.sb_dat_o;
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assign bus.sback = spi_bus.sb_ack_o;
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endmodule
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