Initalized top level design
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@ -1,11 +1,15 @@
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`include "../spi_interface.v"
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`include "../fsm/Fsm.sv"
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<<<<<<< HEAD
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`include "../Bus_if/Bus_if.sv"
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=======
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>>>>>>> b8d8341 (Initalized top level design)
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module Top(
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input wire clk
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);
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// Bus (Interface)
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<<<<<<< HEAD
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Bus_if bus(.clk(clk));
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// SPI Interface
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// FSM
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@ -18,6 +22,10 @@ module Top(
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.outSendData(bus.SendData),
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.outTimerEN(bus.TimerEN)
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);
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=======
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// SPI Interface
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// FSM
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>>>>>>> b8d8341 (Initalized top level design)
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// Parallelport
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// FRAM-Controller
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// Timer
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