Created bus as interface

Bus_if/Bus_if.sv

+interface Bus_if (input clk);
+    logic sbclk;
+    logic sbstb;
+    logic sbrw;
+    logic[7:0] sbadr;
+    logic[7:0] sbdat_r;
+    logic[7:0] sbdat_w;
+    logic sback;
+    logic[9:0] Data;
+    logic SendData;
+    logic TimerMeas;
+    logic Clk;
+    logic DataValid;
+    logic AlarmAmpel;
+    logic TasteAktiv;
+    logic Alarm_R;
+    logic TimerEN;
+    logic Taste;
+    logic ReadTemp;
+    logic LEDg;
+    logic LEDr;
+endinterface //Bus