kuntzschcl/ESY1_Projekt_2022
kuntzschcl/ESY1_Projekt_2022
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Verbesserte TB

Browse Source 
#100000000 muss öfter aufgerufen werden, sonst zahl zu groß
tb ist noch nicht einmal komplett durchgelaufen
This commit is contained in:
Julian Uebler 2022-06-17 10:58:29 +00:00
parent 15b48049ab
commit c7c804a5f9
1 changed files with 128 additions and 107 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

235
Top/random_tl.sv
View File

@ -1,107 +1,128 @@
// Project: ESY-Praktikum-Testbench // Project: ESY-Praktikum-Testbench
// File: random_tl.sv // File: random_tl.sv
// Title: Random Testbench Toplevel // Title: Random Testbench Toplevel
// Description: Creates a Testbench that tests the Toplevel-Design with random based verifikation // Description: Creates a Testbench that tests the Toplevel-Design with random based verifikation
// //
// //
// -------------------------------------------------------------------- // --------------------------------------------------------------------
// //
//------------------------------------------------------------ //------------------------------------------------------------
// Notes: // Notes:
// //
// //
//------------------------------------------------------------ //------------------------------------------------------------
// Development History: // Development History:
// //
// __DATE__ _BY_ _REV_ _DESCRIPTION___________________________ // __DATE__ _BY_ _REV_ _DESCRIPTION___________________________
// 14/06/22 JU/TL 1.0 Initial testbench design // 14/06/22 JU/TL 1.0 Initial testbench design
// //
//------------------------------------------------------------ //------------------------------------------------------------
// Dependencies: // Dependencies:
// Toplevel-Design // Toplevel-Design
// //
// //
//------------------------------------------------------------ //------------------------------------------------------------
//------------------------------------------------------------ //------------------------------------------------------------
// //
// //
// Testbench // Testbench
// //
//------------------------------------------------------------ //------------------------------------------------------------
class Taster_rnd; class Taster_rnd;
rand bit [1:0] data; rand bit [1:0] data;
constraint Rst_rnd constraint Rst_rnd
{ {
data dist {0:=70,1 :=30}; data dist {0:=70,1 :=30};
} }
endclass endclass
class Data_ADC_rnd; class Data_ADC_rnd;
rand bit [7:0] data; rand bit [7:0] data;
endclass endclass
`timescale 1ns/1ps `timescale 1ns/1ps
module testbench_toplevel_rnd; module tb;
// inputs and outputs // inputs and outputs
reg taster; reg taster;
reg [7:0]data_ADC; reg [7:0]data_ADC;
reg clk12M; reg clk12M;
wire RED; wire RED;
wire GRN; wire GRN;
wire alarm; wire alarm;
wire SI; wire alarm_r;
wire SO; wire SI;
wire SCK; wire SO;
wire nCS; wire SCK;
wire nCS;
//random reg endOfConvRnd;
Taster_rnd taster_rnd = new();
Data_ADC_rnd data_ADC_rnd = new(); //random
Taster_rnd taster_rnd = new();
// connect module Data_ADC_rnd data_ADC_rnd = new();
SPI_FRAM_Module fram_storage(.SI(SI),.SO(SO),.SCK(SCK),.nCS(nCS).opcode().addr(),.mem_data(),.stat_reg,.hibernate());
// connect module
initial SPI_FRAM_Module fram_storage(
begin .SI(SI),
clk12M=1'b0; .SO(SO),
end .SCK(SCK),
always .nCS(nCS),.opcode(),.addr());
#41.666666 clk12M=~clk12M; //clock generation Top top(.clk(clk12M),.rst(taster),.endOfConv(endOfConvRnd),.LEDg(GRN),.LEDr(RED),.AlarmAmpel(alarm),.Alarm_R(alarm_r));
//random test initial
initial begin begin
repeat (50) begin clk12M=1'b0;
#50000 end
always
Data_ADC_rnd.randomize(); #41.666666 clk12M=~clk12M; //clock generation
Taster_rnd.randomize();
//random test
taster = taster_rnd.data; initial begin
data_ADC = data_ADC_rnd.data; endOfConvRnd = 1;
repeat (2) begin
// assertions #100000000
#100000000
// assert color green #100000000
assert property(@(posedge clk12M) disable iff (alarm) ((data_ADC < 100) |=> ##4 (!RED && GRN)); #100000000
#100000000
//assert color yellow #100000000
#100000000
assert property(@(posedge clk12M) disable iff (alarm) ((data_ADC >= 100) && (data_ADC <= 168))|=> ##4 (RED && GRN)); #100000000
#100000000
//assert color red + alarm #100000000
data_ADC_rnd.randomize();
assert property(@(posedge clk12M) (data_ADC > 168) |=> ##4 (RED && !GRN && alarm)); taster_rnd.randomize();
$monitor("time=%t, data_ADC=%d, RED=%d, GRN=%d, taster=%d",$time,data_ADC, RED, GRN, taster); taster = taster_rnd.data;
end data_ADC = data_ADC_rnd.data;
$stop;
end
// assertions
endmodule
// assert color green
assert property(@(posedge clk12M) disable iff (alarm | alarm_r) ((data_ADC < 100) |=> ##4 (!RED && GRN)));
//assert color yellow
assert property(@(posedge clk12M) disable iff (alarm | alarm_r) (((data_ADC >= 100) && (data_ADC <= 168))|=> ##4 (RED && GRN)));
//assert color red + alarm
assert property(@(posedge clk12M) disable iff (alarm_r) (data_ADC > 168) |=> ##4 (RED && !GRN && alarm));
//assert alarm reset working
assert property(@(posedge clk12M) (alarm_r |=> ##4 (!RED && !GRN && !alarm)));
$monitor("time=%t, data_ADC=%d, RED=%d, GRN=%d, taster=%d",$time,data_ADC, RED, GRN, taster);
end
$stop;
end
endmodule