Added bus_if and fsm to top level design

Top/Top.sv

 `include "../spi_interface.v"
 `include "../fsm/Fsm.sv"
-<<<<<<< HEAD
-=======
->>>>>>> b8d834144be80086a32a76f1769deccce6eaee15
+`include "../Bus_if/Bus_if.sv"
 
 module Top(
     input wire clk
 );
     // Bus (Interface)
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-
-=======
+    Bus_if bus(.clk(clk));
     // SPI Interface
     // FSM
->>>>>>> b8d834144be80086a32a76f1769deccce6eaee15
+    Fsm fsm(
+        .clk(clk),
+        .inAlarmAmpel(bus.AlarmAmpel),
+        .inDataValid(bus.DataValid),
+        .inTasteAktiv(bus.TasteAktiv),
+        .outAlarm_R(bus.Alarm_R),
+        .outSendData(bus.SendData),
+        .outTimerEN(bus.TimerEN)
+    );
     // Parallelport
     // FRAM-Controller
     // Timer