kuntzschcl/ESY1_Projekt_2022
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merge konflikt behoben

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sessleral71711 2022-06-14 11:52:04 +02:00
parent 6a72019f25
commit ecd6f16dbe
1 changed files with 1 additions and 13 deletions
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14
Top/Top.sv
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@ -1,7 +1,6 @@
`include "../spi_interface.v" `include "../spi_interface.v"
`include "../fsm/Fsm.sv" `include "../fsm/Fsm.sv"
<<<<<<< HEAD <<<<<<< HEAD
`include "../Bus_if/Bus_if.sv"
======= =======
>>>>>>> b8d8341 (Initalized top level design) >>>>>>> b8d8341 (Initalized top level design)
@ -10,18 +9,7 @@ module Top(
); );
// Bus (Interface) // Bus (Interface)
<<<<<<< HEAD <<<<<<< HEAD
Bus_if bus(.clk(clk));
// SPI Interface
// FSM
Fsm fsm(
.clk(clk),
.inAlarmAmpel(bus.AlarmAmpel),
.inDataValid(bus.DataValid),
.inTasteAktiv(bus.TasteAktiv),
.outAlarm_R(bus.Alarm_R),
.outSendData(bus.SendData),
.outTimerEN(bus.TimerEN)
);
======= =======
// SPI Interface // SPI Interface
// FSM // FSM