#100000000 muss öfter aufgerufen werden, sonst zahl zu groß tb ist noch nicht einmal komplett durchgelaufen
129 lines
2.7 KiB
Systemverilog
129 lines
2.7 KiB
Systemverilog
// Project: ESY-Praktikum-Testbench
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// File: random_tl.sv
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// Title: Random Testbench Toplevel
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// Description: Creates a Testbench that tests the Toplevel-Design with random based verifikation
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//
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//
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// --------------------------------------------------------------------
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//
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//------------------------------------------------------------
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// Notes:
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//
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//
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//------------------------------------------------------------
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// Development History:
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//
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// __DATE__ _BY_ _REV_ _DESCRIPTION___________________________
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// 14/06/22 JU/TL 1.0 Initial testbench design
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//
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//------------------------------------------------------------
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// Dependencies:
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// Toplevel-Design
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//
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//
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//------------------------------------------------------------
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//------------------------------------------------------------
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//
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//
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// Testbench
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//
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//------------------------------------------------------------
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class Taster_rnd;
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rand bit [1:0] data;
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constraint Rst_rnd
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{
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data dist {0:=70,1 :=30};
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}
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endclass
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class Data_ADC_rnd;
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rand bit [7:0] data;
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endclass
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`timescale 1ns/1ps
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module tb;
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// inputs and outputs
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reg taster;
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reg [7:0]data_ADC;
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reg clk12M;
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wire RED;
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wire GRN;
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wire alarm;
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wire alarm_r;
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wire SI;
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wire SO;
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wire SCK;
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wire nCS;
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reg endOfConvRnd;
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//random
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Taster_rnd taster_rnd = new();
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Data_ADC_rnd data_ADC_rnd = new();
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// connect module
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SPI_FRAM_Module fram_storage(
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.SI(SI),
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.SO(SO),
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.SCK(SCK),
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.nCS(nCS),.opcode(),.addr());
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Top top(.clk(clk12M),.rst(taster),.endOfConv(endOfConvRnd),.LEDg(GRN),.LEDr(RED),.AlarmAmpel(alarm),.Alarm_R(alarm_r));
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initial
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begin
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clk12M=1'b0;
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end
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always
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#41.666666 clk12M=~clk12M; //clock generation
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//random test
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initial begin
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endOfConvRnd = 1;
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repeat (2) begin
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#100000000
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#100000000
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#100000000
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#100000000
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#100000000
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#100000000
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#100000000
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#100000000
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#100000000
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#100000000
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data_ADC_rnd.randomize();
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taster_rnd.randomize();
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taster = taster_rnd.data;
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data_ADC = data_ADC_rnd.data;
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// assertions
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// assert color green
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assert property(@(posedge clk12M) disable iff (alarm | alarm_r) ((data_ADC < 100) |=> ##4 (!RED && GRN)));
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//assert color yellow
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assert property(@(posedge clk12M) disable iff (alarm | alarm_r) (((data_ADC >= 100) && (data_ADC <= 168))|=> ##4 (RED && GRN)));
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//assert color red + alarm
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assert property(@(posedge clk12M) disable iff (alarm_r) (data_ADC > 168) |=> ##4 (RED && !GRN && alarm));
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//assert alarm reset working
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assert property(@(posedge clk12M) (alarm_r |=> ##4 (!RED && !GRN && !alarm)));
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$monitor("time=%t, data_ADC=%d, RED=%d, GRN=%d, taster=%d",$time,data_ADC, RED, GRN, taster);
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end
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$stop;
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end
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endmodule
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