44 Commits (main)
 

Author SHA1 Message Date
  Christoph Reuss 6a86450a97 Kommentare in Sourcecode ergänzt 1 year ago
  Julian Uebler c7c804a5f9 Verbesserte TB 1 year ago
  sessleral71711 15b48049ab Added SPI interface to top level design 1 year ago
  sessleral71711 97113a9804 modports angepasst 1 year ago
  Ralph Badenberg 71fd941588 modports angepasst 1 year ago
  Julian Uebler a27d049f76 Anfänge einer Tl-TB 1 year ago
  sessleral71711 17f361ea12 I hate git 1 year ago
  sessleral71711 730cc895b1 Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design 1 year ago
  sessleral71711 019dc2868e Added parallelport, timer and ampelsteuerung 1 year ago
  sessleral71711 b30efd039d Added bus_if and fsm to top level design 1 year ago
  sessleral71711 ecd6f16dbe merge konflikt behoben 1 year ago
  sessleral71711 6a72019f25 Initalized top level design 1 year ago
  sessleral71711 53868c67fd Added Bus_if and fsm to top level design 1 year ago
  sessleral71711 6ab278694e Initalized top level design 1 year ago
  sessleral71711 026899b930 Added parallelport, timer and ampelsteuerung 1 year ago
  Ralph Badenberg 9ffb72cf97 Screenshots from RADIANT --> how to create SPI module with radiant 1 year ago
  Ralph Badenberg 72c964475f Screenshots from RADIANT --> how to create SPI module with radiant 1 year ago
  sessleral71711 d2aa8277c7 spi_interface dateien 1 year ago
  sessleral71711 c93bdaf629 Added bus_if and fsm to top level design 1 year ago
  sessleral71711 1be3ce1cea merge konflikt behoben 1 year ago
  sessleral71711 4b0451fc63 Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design 1 year ago
  sessleral71711 20f8e707bd Added Bus_if and fsm to top level design 1 year ago
  Ralph Badenberg c46a1c3b33 add "spi_interface_portsI()" (beginning of document) 1 year ago
  sessleral71711 6b874ba5c7 Initalized top level design 1 year ago
  sessleral71711 200a989683 Added modport for timer 1 year ago
  sessleral71711 613bffbcfc Added modport in Bus_if for Fsm 1 year ago
  Christoph Reuss 19177edb3f Merge branch 'main' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 1 year ago
  Christoph Reuss 0ecac8324e Timer and Port source 1 year ago
  Julian Uebler 37989e5bc1 Ampel 1 year ago
  sessleral71711 ad550a9ac6 Created bus as interface 1 year ago
  sessleral71711 b8d834144b Initalized top level design 1 year ago
  sessleral71711 e8af8d04c8 Merge branch 'main' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 1 year ago
  Claus Kuntzsch ca1f1b531c Dateien hochladen nach „“ 1 year ago
  Claus Kuntzsch 7b858e7068 Dateien hochladen nach „“ 1 year ago
  sessleral71711 71b0458554 FSM mit 2 States erstellt und getestet 1 year ago
  Ralph Badenberg 700350608a Dateien hochladen nach „“ 1 year ago
  sessleral71711 48610eeb8c Added Clk_generator 1 year ago
  sessleral71711 dcb19f11aa FSM initial commit 1 year ago
  Kseniia Mikhailova 937da8ec22 Dateien hochladen nach „“ 1 year ago
  Claus Kuntzsch 1cf5934374 „memory.txt“ löschen 1 year ago
  Claus Kuntzsch 667101d7fd „SPI_FRAM_Module.sv“ löschen 1 year ago
  kuntzschcl 08300af99a FRAM 1 year ago
  Claus Kuntzsch f691d1318a Dateien hochladen nach „“ 1 year ago
  kuntzschcl fec9cd1ae0 Create FM25CL64B.pdf 1 year ago