Initalized top level design

This commit is contained in:
sessleral71711 2022-06-14 10:35:05 +02:00
parent 9ffb72cf97
commit 6ab278694e
2 changed files with 20 additions and 0 deletions

15
Top/Top.sv Normal file
View File

@ -0,0 +1,15 @@
`include "../spi_interface.v"
`include "../fsm/Fsm.sv"
module Top(
input wire clk
);
// Bus (Interface)
// SPI Interface
// FSM
// Parallelport
// FRAM-Controller
// Timer
// Ampelsteuerung
endmodule

5
Top/tb_Top.sv Normal file
View File

@ -0,0 +1,5 @@
`include "Top.sv"
module tb_Top;
endmodule