Initalized top level design

2022-06-14 10:35:05 +02:00 · 2022-06-14 10:35:05 +02:00 · 6ab278694e
commit 6ab278694e
parent 9ffb72cf97
2 changed files with 20 additions and 0 deletions
--- a/Top/Top.sv
+++ b/Top/Top.sv
@ -0,0 +1,15 @@
+`include "../spi_interface.v"
+`include "../fsm/Fsm.sv"
+
+module Top(
+    input wire clk
+);
+    // Bus (Interface)
+    // SPI Interface
+    // FSM
+    // Parallelport
+    // FRAM-Controller
+    // Timer
+    // Ampelsteuerung
+    
+endmodule
--- a/Top/tb_Top.sv
+++ b/Top/tb_Top.sv
@ -0,0 +1,5 @@
+`include "Top.sv"
+
+module tb_Top;
+    
+endmodule