Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design

Top/Top.sv

@@ -2,6 +2,7 @@
 `include "../fsm/Fsm.sv"
 <<<<<<< HEAD
 <<<<<<< HEAD
+<<<<<<< HEAD
 =======
 >>>>>>> b8d8341 (Initalized top level design)
 =======
@@ -11,6 +12,10 @@
 =======
 `include "../timer_port/timer_top.sv"
 >>>>>>> 026899b (Added parallelport, timer and ampelsteuerung)
+=======
+`include "../Bus_if/Bus_if.sv"
+`include "../timer_port/timer_top.sv"
+>>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
 
 module Top(
     input wire clk,
@@ -26,8 +31,11 @@ module Top(
     
     // FSM
 <<<<<<< HEAD
+<<<<<<< HEAD
 >>>>>>> b8d8341 (Initalized top level design)
 =======
+=======
+>>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
     Fsm fsm(
         .clk(clk),
         .inAlarmAmpel(bus.AlarmAmpel),
@@ -37,7 +45,10 @@ module Top(
         .outSendData(bus.SendData),
         .outTimerEN(bus.TimerEN)
     );
+<<<<<<< HEAD
 >>>>>>> c93bdaf (Added bus_if and fsm to top level design)
+=======
+>>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
     // Parallelport
     parallelport parallelport1 (
         .inClk(clk),