Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design

Top/Top.sv

@@ -1,11 +1,15 @@
 `include "../spi_interface.v"
 `include "../fsm/Fsm.sv"
+<<<<<<< HEAD
 `include "../Bus_if/Bus_if.sv"
+=======
+>>>>>>> b8d834144be80086a32a76f1769deccce6eaee15
 
 module Top(
     input wire clk
 );
     // Bus (Interface)
+<<<<<<< HEAD
     Bus_if bus(.clk(clk));
     // SPI Interface
     // FSM
@@ -18,6 +22,10 @@ module Top(
         .outSendData(bus.SendData),
         .outTimerEN(bus.TimerEN)
     );
+=======
+    // SPI Interface
+    // FSM
+>>>>>>> b8d834144be80086a32a76f1769deccce6eaee15
     // Parallelport
     // FRAM-Controller
     // Timer