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ESY1_Projekt_2022
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sessleral71711
53868c67fd
Added Bus_if and fsm to top level design
2022-06-14 12:22:52 +02:00
Bus_if
Added modport for timer
2022-06-14 11:23:54 +02:00
Code_FRAM_Speicher
FRAM
2022-05-19 17:02:44 +02:00
fsm
FSM mit 2 States erstellt und getestet
2022-06-02 09:26:16 +02:00
Source_Ampel
Ampel
2022-06-14 08:59:08 +00:00
Source_FRAM_Controller
FRAM
2022-05-19 17:02:44 +02:00
spi_interface_radiant
Screenshots from RADIANT --> how to create SPI module with radiant
2022-06-14 09:59:23 +00:00
timer_port
Timer and Port source
2022-06-14 11:00:38 +02:00
Top
Added Bus_if and fsm to top level design
2022-06-14 12:22:52 +02:00
BUS.PNG
Dateien hochladen nach „“
2022-05-31 10:14:56 +00:00
FM25CL64B.pdf
Create FM25CL64B.pdf
2022-05-19 16:29:56 +02:00
FRAM Kommunikation.docx
Dateien hochladen nach „“
2022-06-02 07:39:05 +00:00
FRAM_Speicher-Modell.pdf
Dateien hochladen nach „“
2022-05-19 14:51:31 +00:00
Projekt_2022.docx
Dateien hochladen nach „“
2022-05-19 14:51:31 +00:00
SPI FRAM Controller.pdf
Dateien hochladen nach „“
2022-05-19 14:51:31 +00:00
Description
Projektdaten für das ESY1B Praktikum im Sommersemester 2022
5
MiB
Languages
SystemVerilog
100%
