kuntzschcl/ESY1_Projekt_2022
kuntzschcl/ESY1_Projekt_2022
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

FSM mit 2 States erstellt und getestet

Browse Source
This commit is contained in:
sessleral71711 2022-06-02 09:26:16 +02:00
parent 48610eeb8c
commit 71b0458554
2 changed files with 74 additions and 74 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

93
fsm/Fsm.sv
View File

@ -1,63 +1,52 @@
module Fsm
(
input wire clk,
input wire tim_ready,
input wire alarm,
output logic adc_en,
output logic tim_en,
output logic fram_c_en,
output logic led_c_en
input wire inAlarmAmpel,
input wire inDataValid,
input wire inTasteAktiv,
output logic outAlarm_R,
output logic outSendData,
output logic outTimerEN
);
real S0 = 0;
real S1 = 1;
real S2 = 2;
real S3 = 3;
real S4 = 4;
real S5 = 5;
real S6 = 6;
logic[2:0] state;
real IDLE = 0;
real ALARM = 1;
logic state;
initial begin
#0 state <= 0;
#0 adc_en <= 0;
#0 tim_en <= 0;
#0 fram_c_en <= 0;
#0 led_c_en <= 0;
#0 state <= IDLE;
#0 outAlarm_R <= 0;
#0 outSendData <= 0;
#0 outTimerEN <= 0;
end
always @(posedge clk) begin
case(state)
S0: begin
adc_en <= 1'b1;
tim_en <= 1'b1;
state <= S1;
end
S1: begin
adc_en <= 1'b0;
tim_en <= 1'b0;
if(tim_ready) begin
fram_c_en <= 1'b1;
led_c_en <= 1'b1;
state <= S2;
end
else begin
// do nothing
end
end
S2: begin
fram_c_en <= 0'b0;
led_c_en <= 0'b0;
if(alarm) begin
// taster
end
else begin
if(tim_ready) begin
end
state <= S0;
end
end
IDLE: begin
if(inDataValid) begin
outSendData <= 1;
end
else begin
outSendData <= 0;
end
if(inAlarmAmpel) begin
outAlarm_R <= 1;
state <= ALARM;
end
end
ALARM: begin
if(inDataValid) begin
outSendData <= 1;
end
else begin
outSendData <= 0;
end
if(inTasteAktiv) begin
outAlarm_R <= 0;
state <= IDLE;
end
end
default: ;
endcase
end
endmodule
endmodule

55
fsm/tb_Fsm.sv
View File

@ -3,39 +3,50 @@
module tb_Fsm;
wire clk;
logic tim_ready;
logic alarm;
wire adc_en;
wire tim_en;
wire fram_c_en;
wire led_c_en;
logic inAlarmAmpel;
logic inDataValid;
logic inTasteAktiv;
wire outAlarm_R;
wire outSendData;
wire outTimerEN;
Clk_generator clk_gen(.clk(clk));
Fsm myfsm
Fsm myfsm
(
.clk(clk),
.tim_ready(tim_ready),
.alarm(alarm),
.adc_en(adc_en),
.tim_en(tim_en),
.fram_c_en(fram_c_en),
.led_c_en(led_c_en)
.inAlarmAmpel(inAlarmAmpel),
.inDataValid(inDataValid),
.inTasteAktiv(inTasteAktiv),
.outAlarm_R(outAlarm_R),
.outSendData(outSendData),
.outTimerEN(outTimerEN)
);
always @(posedge clk) begin
#1 tim_ready <= ~tim_ready;
end
initial begin
$dumpfile("tb_Fsm.vcd");
$dumpvars(0, tb_Fsm);
#50 $finish;
end
initial begin
#0 tim_ready = 1'b0;
#0 alarm = 1'b0;
#0 inAlarmAmpel = 1'b0;
#0 inDataValid = 1'b0;
#0 inTasteAktiv = 1'b0;
end
initial begin
#4 inAlarmAmpel = 1'b1;
#5 inAlarmAmpel = 1'b0;
#8 inDataValid = 1'b1;
#9 inDataValid = 1'b0;
#10 inTasteAktiv = 1'b1;
#11 inTasteAktiv = 1'b0;
end
endmodule
endmodule