kuntzschcl/ESY1_Projekt_2022
kuntzschcl/ESY1_Projekt_2022
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This commit is contained in:
sessleral71711 2022-06-14 12:33:29 +02:00
parent 730cc895b1
commit 17f361ea12
1 changed files with 1 additions and 27 deletions
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28
Top/Top.sv
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@ -1,21 +1,7 @@
`include "../spi_interface.v"
`include "../fsm/Fsm.sv"
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=======
>>>>>>> b8d8341 (Initalized top level design)
=======
`include "../Bus_if/Bus_if.sv"
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>>>>>>> c93bdaf (Added bus_if and fsm to top level design)
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`include "../timer_port/timer_top.sv"
>>>>>>> 026899b (Added parallelport, timer and ampelsteuerung)
=======
`include "../Bus_if/Bus_if.sv"
`include "../timer_port/timer_top.sv"
>>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
module Top(
input wire clk,
@ -28,14 +14,7 @@ module Top(
// Bus (Interface)
Bus_if bus(.clk(clk));
// SPI Interface
// FSM
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>>>>>>> b8d8341 (Initalized top level design)
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>>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
Fsm fsm(
.clk(clk),
.inAlarmAmpel(bus.AlarmAmpel),
@ -45,10 +24,6 @@ module Top(
.outSendData(bus.SendData),
.outTimerEN(bus.TimerEN)
);
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>>>>>>> c93bdaf (Added bus_if and fsm to top level design)
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>>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
// Parallelport
parallelport parallelport1 (
.inClk(clk),
@ -78,6 +53,5 @@ module Top(
.alarm(bus.AlarmAmpel)
);
assign AlarmAmpel = bus.AlarmAmpel;
assign AlarmAmpel = bus.AlarmAmpel;
endmodule