I hate git

Top/Top.sv

@@ -1,21 +1,7 @@
 `include "../spi_interface.v"
 `include "../fsm/Fsm.sv"
-<<<<<<< HEAD
-<<<<<<< HEAD
-<<<<<<< HEAD
-=======
->>>>>>> b8d8341 (Initalized top level design)
-=======
 `include "../Bus_if/Bus_if.sv"
-<<<<<<< HEAD
->>>>>>> c93bdaf (Added bus_if and fsm to top level design)
-=======
 `include "../timer_port/timer_top.sv"
->>>>>>> 026899b (Added parallelport, timer and ampelsteuerung)
-=======
-`include "../Bus_if/Bus_if.sv"
-`include "../timer_port/timer_top.sv"
->>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
 
 module Top(
     input wire clk,
@@ -28,14 +14,7 @@ module Top(
     // Bus (Interface)
     Bus_if bus(.clk(clk));
     // SPI Interface
-    
     // FSM
-<<<<<<< HEAD
-<<<<<<< HEAD
->>>>>>> b8d8341 (Initalized top level design)
-=======
-=======
->>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
     Fsm fsm(
         .clk(clk),
         .inAlarmAmpel(bus.AlarmAmpel),
@@ -45,10 +24,6 @@ module Top(
         .outSendData(bus.SendData),
         .outTimerEN(bus.TimerEN)
     );
-<<<<<<< HEAD
->>>>>>> c93bdaf (Added bus_if and fsm to top level design)
-=======
->>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
     // Parallelport
     parallelport parallelport1 (
         .inClk(clk),
@@ -78,6 +53,5 @@ module Top(
         .alarm(bus.AlarmAmpel)
     );
 
-    assign AlarmAmpel = bus.AlarmAmpel;
-    
+    assign AlarmAmpel = bus.AlarmAmpel;  
 endmodule