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  • 6a86450 (main) Kommentare in Sourcecode ergänzt by Christoph Reuß 2022-06-22 21:02:47 +0200
  • c7c804a Verbesserte TB by Julian Uebler 2022-06-17 10:58:29 +0000
  • 15b4804 Added SPI interface to top level design by sessleral71711 2022-06-17 11:58:02 +0200
  • 97113a9 modports angepasst by sessleral71711 2022-06-17 11:49:26 +0200
  • 71fd941 modports angepasst by Ralph Badenberg 2022-06-17 09:42:53 +0000
  • a27d049 Anfänge einer Tl-TB by Julian Uebler 2022-06-14 10:53:32 +0000
  • 17f361e (top_level_design) I hate git by sessleral71711 2022-06-14 12:33:29 +0200
  • 730cc89 Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design by sessleral71711 2022-06-14 12:32:53 +0200
  • 019dc28 Added parallelport, timer and ampelsteuerung by sessleral71711 2022-06-14 12:21:25 +0200
  • b30efd0 Added bus_if and fsm to top level design by sessleral71711 2022-06-14 11:53:20 +0200
  • ecd6f16 merge konflikt behoben by sessleral71711 2022-06-14 11:52:04 +0200
  • 6a72019 Initalized top level design by sessleral71711 2022-06-14 10:35:05 +0200
  • 53868c6 Added Bus_if and fsm to top level design by sessleral71711 2022-06-14 11:45:29 +0200
  • 6ab2786 Initalized top level design by sessleral71711 2022-06-14 10:35:05 +0200
  • 026899b Added parallelport, timer and ampelsteuerung by sessleral71711 2022-06-14 12:21:25 +0200
  • 9ffb72c Screenshots from RADIANT --> how to create SPI module with radiant by Ralph Badenberg 2022-06-14 09:59:23 +0000
  • 72c9644 Screenshots from RADIANT --> how to create SPI module with radiant by Ralph Badenberg 2022-06-14 09:58:24 +0000
  • d2aa827 spi_interface dateien by sessleral71711 2022-06-14 11:56:42 +0200
  • c93bdaf Added bus_if and fsm to top level design by sessleral71711 2022-06-14 11:53:20 +0200
  • 1be3ce1 merge konflikt behoben by sessleral71711 2022-06-14 11:52:04 +0200
  • 4b0451f Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design by sessleral71711 2022-06-14 11:51:22 +0200
  • 20f8e70 Added Bus_if and fsm to top level design by sessleral71711 2022-06-14 11:45:29 +0200
  • c46a1c3 add "spi_interface_portsI()" (beginning of document) by Ralph Badenberg 2022-06-14 09:42:25 +0000
  • 6b874ba Initalized top level design by sessleral71711 2022-06-14 10:35:05 +0200
  • 200a989 Added modport for timer by sessleral71711 2022-06-14 11:23:54 +0200
  • 613bffb Added modport in Bus_if for Fsm by sessleral71711 2022-06-14 11:03:41 +0200
  • 19177ed Merge branch 'main' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 by Christoph Reuß 2022-06-14 11:01:22 +0200
  • 0ecac83 Timer and Port source by Christoph Reuß 2022-06-14 11:00:38 +0200
  • 37989e5 Ampel by Julian Uebler 2022-06-14 08:59:08 +0000
  • ad550a9 Created bus as interface by sessleral71711 2022-06-14 10:49:23 +0200
  • b8d8341 Initalized top level design by sessleral71711 2022-06-14 10:35:05 +0200
  • e8af8d0 Merge branch 'main' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 by sessleral71711 2022-06-14 09:51:22 +0200
  • ca1f1b5 Dateien hochladen nach „“ by Claus Kuntzsch 2022-06-02 07:39:05 +0000
  • 7b858e7 Dateien hochladen nach „“ by Claus Kuntzsch 2022-06-02 07:38:28 +0000
  • 71b0458 FSM mit 2 States erstellt und getestet by sessleral71711 2022-06-02 09:26:16 +0200
  • 7003506 Dateien hochladen nach „“ by Ralph Badenberg 2022-05-31 10:58:28 +0000
  • 48610ee Added Clk_generator by sessleral71711 2022-05-31 12:50:05 +0200
  • dcb19f1 FSM initial commit by sessleral71711 2022-05-31 12:45:24 +0200
  • 937da8e Dateien hochladen nach „“ by Kseniia Mikhailova 2022-05-31 10:14:56 +0000
  • 1cf5934 „memory.txt“ löschen by Claus Kuntzsch 2022-05-19 15:04:29 +0000
  • 667101d „SPI_FRAM_Module.sv“ löschen by Claus Kuntzsch 2022-05-19 15:04:22 +0000
  • 08300af FRAM by kuntzschcl 2022-05-19 17:02:44 +0200
  • f691d13 Dateien hochladen nach „“ by Claus Kuntzsch 2022-05-19 14:51:31 +0000
  • fec9cd1 Create FM25CL64B.pdf by kuntzschcl 2022-05-19 16:29:56 +0200