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• 6a86450a97 Kommentare in Sourcecode ergänzt main Christoph Reuß 2022-06-22 21:02:47 +02:00
• c7c804a5f9 Verbesserte TB Julian Uebler 2022-06-17 10:58:29 +00:00
• 15b48049ab Added SPI interface to top level design sessleral71711 2022-06-17 11:58:02 +02:00
• 97113a9804 modports angepasst sessleral71711 2022-06-17 11:49:26 +02:00
• 71fd941588 modports angepasst Ralph Badenberg 2022-06-17 09:42:53 +00:00
• a27d049f76 Anfänge einer Tl-TB Julian Uebler 2022-06-14 10:53:32 +00:00
• 17f361ea12 I hate git top_level_design sessleral71711 2022-06-14 12:33:29 +02:00
• 730cc895b1 Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design sessleral71711 2022-06-14 12:32:53 +02:00
• 019dc2868e Added parallelport, timer and ampelsteuerung sessleral71711 2022-06-14 12:21:25 +02:00
• b30efd039d Added bus_if and fsm to top level design sessleral71711 2022-06-14 11:53:20 +02:00
• ecd6f16dbe merge konflikt behoben sessleral71711 2022-06-14 11:52:04 +02:00
• 6a72019f25 Initalized top level design sessleral71711 2022-06-14 10:35:05 +02:00
• 53868c67fd Added Bus_if and fsm to top level design sessleral71711 2022-06-14 11:45:29 +02:00
• 6ab278694e Initalized top level design sessleral71711 2022-06-14 10:35:05 +02:00
• 026899b930 Added parallelport, timer and ampelsteuerung sessleral71711 2022-06-14 12:21:25 +02:00
• 9ffb72cf97 Screenshots from RADIANT --> how to create SPI module with radiant Ralph Badenberg 2022-06-14 09:59:23 +00:00
• 72c964475f Screenshots from RADIANT --> how to create SPI module with radiant Ralph Badenberg 2022-06-14 09:58:24 +00:00
• d2aa8277c7 spi_interface dateien sessleral71711 2022-06-14 11:56:42 +02:00
• c93bdaf629 Added bus_if and fsm to top level design sessleral71711 2022-06-14 11:53:20 +02:00
• 1be3ce1cea merge konflikt behoben sessleral71711 2022-06-14 11:52:04 +02:00
• 4b0451fc63 Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design sessleral71711 2022-06-14 11:51:22 +02:00
• 20f8e707bd Added Bus_if and fsm to top level design sessleral71711 2022-06-14 11:45:29 +02:00
• c46a1c3b33 add "spi_interface_portsI()" (beginning of document) Ralph Badenberg 2022-06-14 09:42:25 +00:00
• 6b874ba5c7 Initalized top level design sessleral71711 2022-06-14 10:35:05 +02:00
• 200a989683 Added modport for timer sessleral71711 2022-06-14 11:23:54 +02:00
• 613bffbcfc Added modport in Bus_if for Fsm sessleral71711 2022-06-14 11:03:41 +02:00
• 19177edb3f Merge branch 'main' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 Christoph Reuß 2022-06-14 11:01:22 +02:00
• 0ecac8324e Timer and Port source Christoph Reuß 2022-06-14 11:00:38 +02:00
• 37989e5bc1 Ampel Julian Uebler 2022-06-14 08:59:08 +00:00
• ad550a9ac6 Created bus as interface sessleral71711 2022-06-14 10:49:23 +02:00
• b8d834144b Initalized top level design sessleral71711 2022-06-14 10:35:05 +02:00
• e8af8d04c8 Merge branch 'main' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 sessleral71711 2022-06-14 09:51:22 +02:00
• ca1f1b531c Dateien hochladen nach „“ Claus Kuntzsch 2022-06-02 07:39:05 +00:00
• 7b858e7068 Dateien hochladen nach „“ Claus Kuntzsch 2022-06-02 07:38:28 +00:00
• 71b0458554 FSM mit 2 States erstellt und getestet sessleral71711 2022-06-02 09:26:16 +02:00
• 700350608a Dateien hochladen nach „“ Ralph Badenberg 2022-05-31 10:58:28 +00:00
• 48610eeb8c Added Clk_generator sessleral71711 2022-05-31 12:50:05 +02:00
• dcb19f11aa FSM initial commit sessleral71711 2022-05-31 12:45:24 +02:00
• 937da8ec22 Dateien hochladen nach „“ Kseniia Mikhailova 2022-05-31 10:14:56 +00:00
• 1cf5934374 „memory.txt“ löschen Claus Kuntzsch 2022-05-19 15:04:29 +00:00
• 667101d7fd „SPI_FRAM_Module.sv“ löschen Claus Kuntzsch 2022-05-19 15:04:22 +00:00
• 08300af99a FRAM kuntzschcl 2022-05-19 17:02:44 +02:00
• f691d1318a Dateien hochladen nach „“ Claus Kuntzsch 2022-05-19 14:51:31 +00:00
• fec9cd1ae0 Create FM25CL64B.pdf kuntzschcl 2022-05-19 16:29:56 +02:00