ESY1_Projekt_2022/fsm/tb_Fsm.sv

`include "Clk_generator.sv"
`include "Fsm.sv"

module tb_Fsm;
    wire clk;
    logic inAlarmAmpel;
    logic inDataValid;
    logic inTasteAktiv;
    wire outAlarm_R;
    wire outSendData;
    wire outTimerEN;

    Clk_generator clk_gen(.clk(clk));

    Fsm myfsm
    (
      .clk(clk),
      .inAlarmAmpel(inAlarmAmpel),
      .inDataValid(inDataValid),
      .inTasteAktiv(inTasteAktiv),
      .outAlarm_R(outAlarm_R),
      .outSendData(outSendData),
      .outTimerEN(outTimerEN)
    );


    initial begin
        $dumpfile("tb_Fsm.vcd");
        $dumpvars(0, tb_Fsm);
        #50 $finish;
    end

    initial begin
        #0 inAlarmAmpel = 1'b0;
        #0 inDataValid = 1'b0;
        #0 inTasteAktiv = 1'b0;
    end
  
   initial begin
        #4 inAlarmAmpel = 1'b1;
        #5 inAlarmAmpel = 1'b0;
     
        #8 inDataValid = 1'b1;
        #9 inDataValid = 1'b0;
     
        #10 inTasteAktiv = 1'b1;
        #11 inTasteAktiv = 1'b0;
    end


endmodule