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timer.sv 1.3KB

1 year ago
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  1. //------------------------------------------------------
  2. //
  3. // File : Timer.sv
  4. // Related Files :
  5. // Author(s) :
  6. // Email :
  7. // Organization : Georg-Simon-Ohm-Hochschule Nuernberg
  8. // Notes :
  9. //
  10. //------------------------------------------------------
  11. // History
  12. //------------------------------------------------------
  13. // Version| Author | Mod. Date | Changes Made:
  14. // v1.00 | | 11.05.2023 |
  15. //------------------------------------------------------
  16. //eoh
  17. module timer(bus.timer_port fpga_bus, clock_if.clock_port_top c); // (bus.timer b, clock_if.clock_port_top i)
  18. integer counter = 0; // internal count reg
  19. integer reload_val;
  20. always @ (posedge c.clk or fpga_bus.dip[0]) begin
  21. if (!fpga_bus.dip[0]) begin
  22. counter <= 0;
  23. fpga_bus.timer <= 0;
  24. end else begin
  25. if(counter <= 800) begin // zu testzwecken kürzer 1000000
  26. counter++;
  27. fpga_bus.timer <= 0;
  28. end else begin
  29. counter <= 0;
  30. fpga_bus.timer <= 1;
  31. end
  32. end
  33. end
  34. //give the input clock on the bus
  35. always@(posedge c.clk or negedge c.clk)
  36. fpga_bus.clk = c.clk;
  37. endmodule : timer