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uebung_projekt

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hans 11 months ago
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uebung_projekt/compilescripts/simulation/compile.tcl View File

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## -------------------------------------------------------------
##
## File : compile.tcl
## Author(s) : Baesig
## Gerstner
## Email : juergen.baesig@fh-nuernberg.de
## Gerstnermi46611@th-nuernberg.de
## Organization : Georg-Simon-Ohm-Hochschule Nuernberg
##
## Note :
##
## -------------------------------------------------------------
## History
## -------------------------------------------------------------
## Version| Author | Mod. Date | Changes Made:
## v1.00 | Baesig | 09/04/2012 | first code
## v1.01 | Gerstner | 20/09/2013 | modified
## -------------------------------------------------------------
##eoh
.main clear
echo
# ----------------------------------------------------------
echo "create workspace"
if [file exists work] { vdel -all }
vlib work
vmap work ./work
echo
# ----------------------------------------------------------
echo " Compile sv-Designfiles "
vlog -work work ./hdl_src/sv/interface.sv
vlog -work work ./hdl_src/sv/stimuli.sv
vlog -work work ./hdl_src/sv/top_level.sv
vlog -work work ./hdl_src/sv/top_tb.sv
vlog -work work ./hdl_src/sv/timer.sv
vlog -work work ./hdl_src/sv/SPI_Master_Control.sv
vlog -work work ./hdl_src/sv/SPI_Master.sv
vlog -work work ./hdl_src/sv/FRAM_Controller.sv
vlog -work work ./hdl_src/sv/fram.sv
echo
# ----------------------------------------------------------
echo " Run Simulation "
source ./simulationsscripts/simulation.tcl

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uebung_projekt/hdl_src/sv/FRAM_Controller.sv View File

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module FRAM(
input i_clk, //Module (Module CLock = SPI Clock)
input i_nreset,
input logic [19:0] i_adr, //Memorycell adress in FRAM
input logic [7:0] i_data, //data to write
output logic [7:0] o_data, //data to read
input logic i_rw, //Read = 1, Write = 0
input logic i_status, //If 1 Read Staut register
input logic i_hbn, //If 1 FRAM will enter Hibernation Mode
input logic i_cready, //Starts transmission
output logic o_busy, //Indicates FRAM Busy
// SPI Interface
output o_SPI_Clk,
input i_SPI_MISO,
output o_SPI_MOSI,
output o_SPI_CS_n

);
//FRAM SPI OP Codes

//Write Enable Control
localparam WREN = 8'h06; //Set Write enable latch
localparam WRDI = 8'h04; //Reset write enable latch
//Register Access
localparam RDSR = 8'h05; //Read Status Register
localparam WRSR = 8'h01; //Write Status Register
//Memory Write
localparam WRITE = 8'h02; //Write Memory Data
//Memory Read
localparam READ = 8'h03; //Read Memory Data
localparam FSTRT = 8'h0B; //Fast read memory Data
//Special Sector Memory Access
localparam SSWR = 8'h42; //Spcial Sector Write
localparam SSRD = 8'h4B; //Special Sector Read
//Identification and serial Number
localparam RDID = 8'h9F; //Read Device ID
localparam RUID = 8'h4C; //Read Unique ID
localparam WRSN = 8'hC2; //Write Serial Number
localparam RDSN = 8'hC3; //Read Serial Number
//Low Power Modes
localparam DPD = 8'hBA; // Enter Deep Power-Down
localparam HBN = 8'hB9; // Enter Hibernate Mode
//end FRAM SPI OP Codes
//Controller Specific
logic [3:0] state;
// SPI Specific
parameter SPI_MODE = 0; // CPOL = 0, CPHA = 0
parameter CLKS_PER_HALF_BIT = 2; // 25MHz
parameter MAX_BYTES_PER_CS = 5; // 5 bytes max per chip select cycle
parameter CS_INACTIVE_CLKS = 1; // Adds delay (1clk) between cycles
logic [7:0] r_Master_TX_Byte = 0;
logic r_Master_TX_DV = 1'b0;
logic w_Master_TX_Ready;
logic w_Master_RX_DV;
logic [7:0] w_Master_RX_Byte;
logic [$clog2(MAX_BYTES_PER_CS+1)-1:0] w_Master_RX_Count, r_Master_TX_Count = 3'h1; //Standard 1 Byte pro CS Cycle
SPI_Master_With_Single_CS
#(.SPI_MODE(SPI_MODE), //SPI Mode 0-3
.CLKS_PER_HALF_BIT(CLKS_PER_HALF_BIT), //sets Frequency of SPI_CLK
.MAX_BYTES_PER_CS(MAX_BYTES_PER_CS), //Maximum Bytes per CS Cycle
.CS_INACTIVE_CLKS(CS_INACTIVE_CLKS) //Amount of Time holding CS Low befor next command
) SPI
(
// Control/Data Signals,
.i_Rst_L(i_nreset), // FPGA Reset
.i_Clk(i_clk), // FPGA Clock
// TX (MOSI) Signals
.i_TX_Count(r_Master_TX_Count), // Number of bytes per CS
.i_TX_Byte(r_Master_TX_Byte), // Byte to transmit on MOSI
.i_TX_DV(r_Master_TX_DV), // Data Valid Pulse with i_TX_Byte
.o_TX_Ready(w_Master_TX_Ready), // Transmit Ready for Byte
// RX (MISO) Signals
.o_RX_Count(w_Master_RX_Count), // Index of RX'd byte
.o_RX_DV(w_Master_RX_DV), // Data Valid pulse (1 clock cycle)
.o_RX_Byte(w_Master_RX_Byte), // Byte received on MISO

// SPI Interface
.o_SPI_Clk(o_SPI_Clk),
.i_SPI_MISO(i_SPI_MISO),
.o_SPI_MOSI(o_SPI_MOSI),
.o_SPI_CS_n(o_SPI_CS_n)
);
//end SPI Specific
task SPI_SendByte(input [7:0] data);
@(posedge i_clk);
r_Master_TX_Byte <= data;
r_Master_TX_DV <= 1'b1;
@(posedge i_clk);
r_Master_TX_DV <= 1'b0;
@(posedge i_clk);
@(posedge w_Master_TX_Ready);
endtask //end SPI_SendByte
//FRAM Tasks
task FRAM_Write(input [19:0] adr, input [7:0] data); //vgl. Fig.11
logic [7:0] value;
value <= 8'h0;
//Set Write Enable
r_Master_TX_Count <= 3'b1; //1Byte Transaction
SPI_SendByte(WREN);
//Write to fram
r_Master_TX_Count <= 3'h5; //5 Byte Transaction
SPI_SendByte(WRITE); //OPCode
SPI_SendByte({4'hF,adr[19:16]}); //Adress [23-16]
SPI_SendByte(adr[15:8]); //Adress [15-8]
SPI_SendByte(adr[7:0]); //Adress [7-0]
SPI_SendByte(data); //Data [7:0]
//Reset Write Disable and Verify
do begin
r_Master_TX_Count <= 3'b1; //1Byte Transaction
SPI_SendByte(WRDI); //Set Write Disable
FRAM_Read_Status(value); //Lese Status Register
end while(((value & 8'h2) >> 1) != 0);
endtask //end FRAM_Write
task FRAM_Read(input [19:0] adr, output [7:0] data); //vgl. Fig12
r_Master_TX_Count <= 3'h5; //5 Byte Transaction
SPI_SendByte(READ); //Opcode
SPI_SendByte({4'hF,adr[19:16]}); //Adress [23-16]
SPI_SendByte(adr[15:8]); //Adress [15-8]
SPI_SendByte(adr[7:0]); //Adress [7-0]
SPI_SendByte(8'hAA); //Dummy Bits, read byte in w_Master_RX_Byte
data = w_Master_RX_Byte;
endtask //end FRAM_READ
task FRAM_Read_Status(output [7:0] data); //vgl. Fig9
r_Master_TX_Count <= 3'h2; //2 Byte Transaction
SPI_SendByte(RDSR); //OpCode
SPI_SendByte(8'hFD); //Dummy Bits, read byte in w_Master_RX_Byte
data = w_Master_RX_Byte;
endtask //FRAM_Read_Status
task FRAM_Hibernation(); //vgl. Fig22
r_Master_TX_Count <= 3'h1; //1 Byte Transaction
SPI_SendByte(HBN);
endtask //FRAM_Hibernation
//end FRAM Tasks
always @(posedge i_clk or negedge i_nreset) begin
state[0] = i_cready;
state[1] = i_hbn;
state[2] = i_status;
state[3] = i_rw;
if(~i_nreset) begin //Modul Reset
o_data <= 8'h00;
end //end if
if(w_Master_TX_Ready) begin
case(state) inside
4'b??11: FRAM_Hibernation();
4'b?101: FRAM_Read_Status(o_data);
4'b1001: FRAM_Read(i_adr, o_data);
4'b0001: FRAM_Write(i_adr, i_data);
default:;
endcase //endcase
end //endif

end //end always
assign o_busy = w_Master_TX_Ready;
endmodule

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uebung_projekt/hdl_src/sv/SPI_Master.sv View File

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///////////////////////////////////////////////////////////////////////////////
//Source: https://github.com/nandland/spi-master/tree/master/Verilog/source
//Description: SPI (Serial Peripheral Interface) Master
// With single chip-select (AKA Slave Select) capability
//
// Supports arbitrary length byte transfers.
//
// Instantiates a SPI Master and adds single CS.
// If multiple CS signals are needed, will need to use different
// module, OR multiplex the CS from this at a higher level.
//
// Note: i_Clk must be at least 2x faster than i_SPI_Clk
//
// Parameters: SPI_MODE, can be 0, 1, 2, or 3. See above.
// Can be configured in one of 4 modes:
// Mode | Clock Polarity (CPOL/CKP) | Clock Phase (CPHA)
// 0 | 0 | 0
// 1 | 0 | 1
// 2 | 1 | 0
// 3 | 1 | 1
//
// CLKS_PER_HALF_BIT - Sets frequency of o_SPI_Clk. o_SPI_Clk is
// derived from i_Clk. Set to integer number of clocks for each
// half-bit of SPI data. E.g. 100 MHz i_Clk, CLKS_PER_HALF_BIT = 2
// would create o_SPI_CLK of 25 MHz. Must be >= 2
//
// MAX_BYTES_PER_CS - Set to the maximum number of bytes that
// will be sent during a single CS-low pulse.
//
// CS_INACTIVE_CLKS - Sets the amount of time in clock cycles to
// hold the state of Chip-Selct high (inactive) before next
// command is allowed on the line. Useful if chip requires some
// time when CS is high between trasnfers.
///////////////////////////////////////////////////////////////////////////////



module SPI_Master_With_Single_CS
#(parameter SPI_MODE = 0,
parameter CLKS_PER_HALF_BIT = 2,
parameter MAX_BYTES_PER_CS = 1,
parameter CS_INACTIVE_CLKS = 1)
(
// Control/Data Signals,
input i_Rst_L, // FPGA Reset
input i_Clk, // FPGA Clock
// TX (MOSI) Signals
input [$clog2(MAX_BYTES_PER_CS+1)-1:0] i_TX_Count, // # bytes per CS low
input [7:0] i_TX_Byte, // Byte to transmit on MOSI
input i_TX_DV, // Data Valid Pulse with i_TX_Byte
output o_TX_Ready, // Transmit Ready for next byte
// RX (MISO) Signals
output reg [$clog2(MAX_BYTES_PER_CS+1)-1:0] o_RX_Count, // Index RX byte
output o_RX_DV, // Data Valid pulse (1 clock cycle)
output [7:0] o_RX_Byte, // Byte received on MISO

// SPI Interface
output o_SPI_Clk,
input i_SPI_MISO,
output o_SPI_MOSI,
output o_SPI_CS_n
);

localparam IDLE = 2'b00;
localparam TRANSFER = 2'b01;
localparam CS_INACTIVE = 2'b10;

reg [1:0] r_SM_CS;
reg r_CS_n;
reg [$clog2(CS_INACTIVE_CLKS)-1:0] r_CS_Inactive_Count;
reg [$clog2(MAX_BYTES_PER_CS+1)-1:0] r_TX_Count;
wire w_Master_Ready;

// Instantiate Master
SPI_Master
#(.SPI_MODE(SPI_MODE),
.CLKS_PER_HALF_BIT(CLKS_PER_HALF_BIT)
) SPI_Master_Inst
(
// Control/Data Signals,
.i_Rst_L(i_Rst_L), // FPGA Reset
.i_Clk(i_Clk), // FPGA Clock
// TX (MOSI) Signals
.i_TX_Byte(i_TX_Byte), // Byte to transmit
.i_TX_DV(i_TX_DV), // Data Valid Pulse
.o_TX_Ready(w_Master_Ready), // Transmit Ready for Byte
// RX (MISO) Signals
.o_RX_DV(o_RX_DV), // Data Valid pulse (1 clock cycle)
.o_RX_Byte(o_RX_Byte), // Byte received on MISO

// SPI Interface
.o_SPI_Clk(o_SPI_Clk),
.i_SPI_MISO(i_SPI_MISO),
.o_SPI_MOSI(o_SPI_MOSI)
);


// Purpose: Control CS line using State Machine
always @(posedge i_Clk or negedge i_Rst_L)
begin
if (~i_Rst_L)
begin
r_SM_CS <= IDLE;
r_CS_n <= 1'b1; // Resets to high
r_TX_Count <= 0;
r_CS_Inactive_Count <= CS_INACTIVE_CLKS;
end
else
begin

case (r_SM_CS)
IDLE:
begin
if (r_CS_n & i_TX_DV) // Start of transmission
begin
r_TX_Count <= i_TX_Count - 1; // Register TX Count
r_CS_n <= 1'b0; // Drive CS low
r_SM_CS <= TRANSFER; // Transfer bytes
end
end

TRANSFER:
begin
// Wait until SPI is done transferring do next thing
if (w_Master_Ready)
begin
if (r_TX_Count > 0)
begin
if (i_TX_DV)
begin
r_TX_Count <= r_TX_Count - 1;
end
end
else
begin
r_CS_n <= 1'b1; // we done, so set CS high
r_CS_Inactive_Count <= CS_INACTIVE_CLKS;
r_SM_CS <= CS_INACTIVE;
end // else: !if(r_TX_Count > 0)
end // if (w_Master_Ready)
end // case: TRANSFER

CS_INACTIVE:
begin
if (r_CS_Inactive_Count > 0)
begin
r_CS_Inactive_Count <= r_CS_Inactive_Count - 1'b1;
end
else
begin
r_SM_CS <= IDLE;
end
end

default:
begin
r_CS_n <= 1'b1; // we done, so set CS high
r_SM_CS <= IDLE;
end
endcase // case (r_SM_CS)
end
end // always @ (posedge i_Clk or negedge i_Rst_L)


// Purpose: Keep track of RX_Count
always @(posedge i_Clk)
begin
begin
if (r_CS_n)
begin
o_RX_Count <= 0;
end
else if (o_RX_DV)
begin
o_RX_Count <= o_RX_Count + 1'b1;
end
end
end

assign o_SPI_CS_n = r_CS_n;

assign o_TX_Ready = ((r_SM_CS == IDLE) | (r_SM_CS == TRANSFER && w_Master_Ready == 1'b1 && r_TX_Count > 0)) & ~i_TX_DV;

endmodule // SPI_Master_With_Single_CS

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uebung_projekt/hdl_src/sv/SPI_Master_Control.sv View File

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//////////////////////////////////////////////////////////////////////////////
//Source: https://github.com/nandland/spi-master/tree/master/Verilog/source
// Description: SPI (Serial Peripheral Interface) Master
// Creates master based on input configuration.
// Sends a byte one bit at a time on MOSI
// Will also receive byte data one bit at a time on MISO.
// Any data on input byte will be shipped out on MOSI.
//
// To kick-off transaction, user must pulse i_TX_DV.
// This module supports multi-byte transmissions by pulsing
// i_TX_DV and loading up i_TX_Byte when o_TX_Ready is high.
//
// This module is only responsible for controlling Clk, MOSI,
// and MISO. If the SPI peripheral requires a chip-select,
// this must be done at a higher level.
//
// Note: i_Clk must be at least 2x faster than i_SPI_Clk
//
// Parameters: SPI_MODE, can be 0, 1, 2, or 3. See above.
// Can be configured in one of 4 modes:
// Mode | Clock Polarity (CPOL/CKP) | Clock Phase (CPHA)
// 0 | 0 | 0
// 1 | 0 | 1
// 2 | 1 | 0
// 3 | 1 | 1
// More: https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus#Mode_numbers
// CLKS_PER_HALF_BIT - Sets frequency of o_SPI_Clk. o_SPI_Clk is
// derived from i_Clk. Set to integer number of clocks for each
// half-bit of SPI data. E.g. 100 MHz i_Clk, CLKS_PER_HALF_BIT = 2
// would create o_SPI_CLK of 25 MHz. Must be >= 2
//
///////////////////////////////////////////////////////////////////////////////

module SPI_Master
#(parameter SPI_MODE = 0,
parameter CLKS_PER_HALF_BIT = 2)
(
// Control/Data Signals,
input i_Rst_L, // FPGA Reset
input i_Clk, // FPGA Clock
// TX (MOSI) Signals
input [7:0] i_TX_Byte, // Byte to transmit on MOSI
input i_TX_DV, // Data Valid Pulse with i_TX_Byte
output reg o_TX_Ready, // Transmit Ready for next byte
// RX (MISO) Signals
output reg o_RX_DV, // Data Valid pulse (1 clock cycle)
output reg [7:0] o_RX_Byte, // Byte received on MISO

// SPI Interface
output reg o_SPI_Clk,
input i_SPI_MISO,
output reg o_SPI_MOSI
);

// SPI Interface (All Runs at SPI Clock Domain)
wire w_CPOL; // Clock polarity
wire w_CPHA; // Clock phase

reg [$clog2(CLKS_PER_HALF_BIT*2)-1:0] r_SPI_Clk_Count;
reg r_SPI_Clk;
reg [4:0] r_SPI_Clk_Edges;
reg r_Leading_Edge;
reg r_Trailing_Edge;
reg r_TX_DV;
reg [7:0] r_TX_Byte;

reg [2:0] r_RX_Bit_Count;
reg [2:0] r_TX_Bit_Count;

// CPOL: Clock Polarity
// CPOL=0 means clock idles at 0, leading edge is rising edge.
// CPOL=1 means clock idles at 1, leading edge is falling edge.
assign w_CPOL = (SPI_MODE == 2) | (SPI_MODE == 3);

// CPHA: Clock Phase
// CPHA=0 means the "out" side changes the data on trailing edge of clock
// the "in" side captures data on leading edge of clock
// CPHA=1 means the "out" side changes the data on leading edge of clock
// the "in" side captures data on the trailing edge of clock
assign w_CPHA = (SPI_MODE == 1) | (SPI_MODE == 3);



// Purpose: Generate SPI Clock correct number of times when DV pulse comes
always @(posedge i_Clk or negedge i_Rst_L)
begin
if (~i_Rst_L)
begin
o_TX_Ready <= 1'b0;
r_SPI_Clk_Edges <= 0;
r_Leading_Edge <= 1'b0;
r_Trailing_Edge <= 1'b0;
r_SPI_Clk <= w_CPOL; // assign default state to idle state
r_SPI_Clk_Count <= 0;
end
else
begin

// Default assignments
r_Leading_Edge <= 1'b0;
r_Trailing_Edge <= 1'b0;
if (i_TX_DV)
begin
o_TX_Ready <= 1'b0;
r_SPI_Clk_Edges <= 16; // Total # edges in one byte ALWAYS 16
end
else if (r_SPI_Clk_Edges > 0)
begin
o_TX_Ready <= 1'b0;
if (r_SPI_Clk_Count == CLKS_PER_HALF_BIT*2-1)
begin
r_SPI_Clk_Edges <= r_SPI_Clk_Edges - 1;
r_Trailing_Edge <= 1'b1;
r_SPI_Clk_Count <= 0;
r_SPI_Clk <= ~r_SPI_Clk;
end
else if (r_SPI_Clk_Count == CLKS_PER_HALF_BIT-1)
begin
r_SPI_Clk_Edges <= r_SPI_Clk_Edges - 1;
r_Leading_Edge <= 1'b1;
r_SPI_Clk_Count <= r_SPI_Clk_Count + 1;
r_SPI_Clk <= ~r_SPI_Clk;
end
else
begin
r_SPI_Clk_Count <= r_SPI_Clk_Count + 1;
end
end
else
begin
o_TX_Ready <= 1'b1;
end
end // else: !if(~i_Rst_L)
end // always @ (posedge i_Clk or negedge i_Rst_L)


// Purpose: Register i_TX_Byte when Data Valid is pulsed.
// Keeps local storage of byte in case higher level module changes the data
always @(posedge i_Clk or negedge i_Rst_L)
begin
if (~i_Rst_L)
begin
r_TX_Byte <= 8'h00;
r_TX_DV <= 1'b0;
end
else
begin
r_TX_DV <= i_TX_DV; // 1 clock cycle delay
if (i_TX_DV)
begin
r_TX_Byte <= i_TX_Byte;
end
end // else: !if(~i_Rst_L)
end // always @ (posedge i_Clk or negedge i_Rst_L)


// Purpose: Generate MOSI data
// Works with both CPHA=0 and CPHA=1
always @(posedge i_Clk or negedge i_Rst_L)
begin
if (~i_Rst_L)
begin
o_SPI_MOSI <= 1'b0;
r_TX_Bit_Count <= 3'b111; // send MSb first
end
else
begin
// If ready is high, reset bit counts to default
if (o_TX_Ready)
begin
r_TX_Bit_Count <= 3'b111;
end
// Catch the case where we start transaction and CPHA = 0
else if (r_TX_DV & ~w_CPHA)
begin
o_SPI_MOSI <= r_TX_Byte[3'b111];
r_TX_Bit_Count <= 3'b110;
end
else if ((r_Leading_Edge & w_CPHA) | (r_Trailing_Edge & ~w_CPHA))
begin
r_TX_Bit_Count <= r_TX_Bit_Count - 1;
o_SPI_MOSI <= r_TX_Byte[r_TX_Bit_Count];
end
end
end


// Purpose: Read in MISO data.
always @(posedge i_Clk or negedge i_Rst_L)
begin
if (~i_Rst_L)
begin
o_RX_Byte <= 8'h00;
o_RX_DV <= 1'b0;
r_RX_Bit_Count <= 3'b111;
end
else
begin

// Default Assignments
o_RX_DV <= 1'b0;

if (o_TX_Ready) // Check if ready is high, if so reset bit count to default
begin
r_RX_Bit_Count <= 3'b111;
end
else if ((r_Leading_Edge & ~w_CPHA) | (r_Trailing_Edge & w_CPHA))
begin
o_RX_Byte[r_RX_Bit_Count] <= i_SPI_MISO; // Sample data
r_RX_Bit_Count <= r_RX_Bit_Count - 1;
if (r_RX_Bit_Count == 3'b000)
begin
o_RX_DV <= 1'b1; // Byte done, pulse Data Valid
end
end
end
end
// Purpose: Add clock delay to signals for alignment.
always @(posedge i_Clk or negedge i_Rst_L)
begin
if (~i_Rst_L)
begin
o_SPI_Clk <= w_CPOL;
end
else
begin
o_SPI_Clk <= r_SPI_Clk;
end // else: !if(~i_Rst_L)
end // always @ (posedge i_Clk or negedge i_Rst_L)

endmodule // SPI_Master

+ 40
- 0
uebung_projekt/hdl_src/sv/assert_file.txt View File

@@ -0,0 +1,40 @@
//------------------------------------------------------
//
// File : assert_file.sv
// Related Files :
// Author(s) : Mueller
// Email : muelleral82290@th-nuernberg.de
// Organization : Georg-Simon-Ohm-Hochschule Nuernberg
// Notes : Stimuli Modul
//
//------------------------------------------------------
// History
//------------------------------------------------------
// Version| Author | Mod. Date | Changes Made:
// v1.00 | Mueller | 27/04/2023 | first code
//------------------------------------------------------


//properties-> HIER NOCH NICHTS GEMACHT!

/* example
property p_ones;
bus_m.op == 4'h1 |-> bus_m.z == 4'hf;
endproperty

property p_and;
bus_m.op == 4'h4 |-> bus_m.z == (bus_m.a & bus_m.b);
endproperty

//assertions

a_ones : assert property(@(posedge clk) p_ones)
$display("%t, property asserted: a_ones", $time());
else
$display("%t, property failed: a_ones", $time());

a_and : assert property(@(posedge clk) p_and)
$display("%t, property asserted: a_and", $time());
else
$display("%t, property failed: a_and", $time());
*/

+ 86
- 0
uebung_projekt/hdl_src/sv/fram.sv View File

@@ -0,0 +1,86 @@



module spi(bus.spi_port b, fram_if.fram_port_top i);

parameter ringbuffer_size = 256;
logic [19:0] FRAM_Adr;
logic [7:0] FRAM_DATA_OUT;
logic [7:0] FRAM_DATA_IN;
logic FRAM_RW;
logic FRAM_RSTATUS;
logic FRAM_hbn;
logic FRAM_go;
logic FRAM_busy;
logic [7:0] clk_cntr;

initial begin
FRAM_Adr <= 20'h0;
FRAM_DATA_IN <= 8'h0;
FRAM_RW = 0;
FRAM_RSTATUS = 0;
FRAM_hbn = 0;
FRAM_go = 0;
clk_cntr = 0;
end
always @ (posedge b.timer) begin
if(b.dip[0] == 0) begin //Reset
FRAM_Adr <= 20'h0;
FRAM_DATA_IN <= 8'h0;
FRAM_RW = 0;
FRAM_RSTATUS = 0;
FRAM_hbn = 0;
FRAM_go = 0;
clk_cntr = 0;
end
else if(b.dip[1] == 1) begin //Read
FRAM_Adr <= (FRAM_Adr - 1) % (ringbuffer_size - 1);
FRAM_RW <= 1'h1; //Read
FRAM_go <= 1'h1; //Go
end
else if(b.dip[1] == 0) begin //Write
FRAM_Adr <= (FRAM_Adr + 1) % (ringbuffer_size - 1);
FRAM_DATA_IN <= {6'h0, b.dip[3:2]};
FRAM_RW <= 1'h0; //Write Operation
FRAM_go <= 1'h1; //Go
end
end
always @ (posedge b.clk) begin
if(FRAM_go == 1)
clk_cntr <= clk_cntr + 1;
if(clk_cntr > 50 && FRAM_RW == 1'h1) begin
b.spi_read <= FRAM_DATA_OUT[1:0];
FRAM_go <= 1'h0;
FRAM_RW <= 1'h0;
clk_cntr <= 0;
end
else if(clk_cntr > 50 && FRAM_RW == 1'h0) begin
FRAM_go <= 1'h0;
clk_cntr <= 0;
end
end
FRAM FRAM_ut(
.i_clk(b.clk),
.i_nreset(b.dip[0]),
.i_adr(FRAM_Adr),
.i_data(FRAM_DATA_IN),
.o_data(FRAM_DATA_OUT),
.i_rw(FRAM_RW),
.i_status(FRAM_RSTATUS),
.i_hbn(FRAM_hbn),
.i_cready(FRAM_go),
.o_busy(FRAM_busy),
.o_SPI_Clk(i.sclk),
.i_SPI_MISO(i.mosi),
.o_SPI_MOSI(i.mosi),
.o_SPI_CS_n(i.ss)
);
endmodule

+ 86
- 0
uebung_projekt/hdl_src/sv/fram.sv.bak View File

@@ -0,0 +1,86 @@



module spi(bus.spi_port b, fram_if.fram_port_top i);

parameter ringbuffer_size = 256;
logic [19:0] FRAM_Adr;
logic [7:0] FRAM_DATA_OUT;
logic [7:0] FRAM_DATA_IN;
logic FRAM_RW;
logic FRAM_RSTATUS;
logic FRAM_hbn;
logic FRAM_go;
logic FRAM_busy;
logic [7:0] clk_cntr;

initial begin
FRAM_Adr <= 20'h0;
FRAM_DATA_IN <= 8'h0;
FRAM_RW = 0;
FRAM_RSTATUS = 0;
FRAM_hbn = 0;
FRAM_go = 0;
clk_cntr = 0;
end
always @ (posedge b.timer) begin
if(b.dip[0] == 0) begin //Reset
FRAM_Adr <= 20'h0;
FRAM_DATA_IN <= 8'h0;
FRAM_RW = 0;
FRAM_RSTATUS = 0;
FRAM_hbn = 0;
FRAM_go = 0;
clk_cntr = 0;
end
else if(b.dip[1] == 1) begin //Read
FRAM_Adr <= (FRAM_Adr - 1) % (ringbuffer_size - 1);
FRAM_RW <= 1'h1; //Read
FRAM_go <= 1'h1; //Go
end
else if(b.dip[1] == 0) begin //Write
FRAM_Adr <= (FRAM_Adr + 1) % (ringbuffer_size - 1);
FRAM_DATA_IN <= {6'h0, b.dip[3:2]};
FRAM_RW <= 1'h0; //Write Operation
FRAM_go <= 1'h1; //Go
end
end
always @ (posedge b.clk) begin
if(FRAM_go == 1)
clk_cntr <= clk_cntr + 1;
if(clk_cntr > 50 && FRAM_RW == 1'h1) begin
b.spi_read <= FRAM_DATA_OUT[1:0];
FRAM_go <= 1'h0;
FRAM_RW <= 1'h0;
clk_cntr <= 0;
end
else if(clk_cntr > 50 && FRAM_RW == 1'h0) begin
FRAM_go <= 1'h0;
clk_cntr <= 0;
end
end
FRAM FRAM_ut(
.i_clk(b.clk),
.i_nreset(b.dip[0]),
.i_adr(FRAM_Adr),
.i_data(FRAM_DATA_IN),
.o_data(FRAM_DATA_OUT),
.i_rw(FRAM_RW),
.i_status(FRAM_RSTATUS),
.i_hbn(FRAM_hbn),
.i_cready(FRAM_go),
.o_busy(FRAM_busy),
.o_SPI_Clk(i.sclk),
.i_SPI_MISO(i.mosi),
.o_SPI_MOSI(i.mosi),
.o_SPI_CS_n(i.ss)
);
endmodule

+ 69
- 0
uebung_projekt/hdl_src/sv/interface.sv View File

@@ -0,0 +1,69 @@
//------------------------------------------------------
//
// File : interface.sv
// Related Files :
// Author(s) : Mueller
// Email : muelleral82290@th-nuernberg.de
// Organization : Georg-Simon-Ohm-Hochschule Nuernberg
// Notes : Stimuli Modul
//
//------------------------------------------------------
// History
//------------------------------------------------------
// Version| Author | Mod. Date | Changes Made:
// v1.00 | Mueller | 11/05/2023 | first code
//------------------------------------------------------
//eoh
//interface for LED
//reg [2:0]rbg stores rgb values that depend on dip[3:2]
interface led_if();
logic [2:0]rgb;
modport led_port_stim(input rgb);
modport led_port_top(output rgb);
endinterface : led_if
//interface for DIPSCHALER
// dip[3:2] -> select colour, dip[1] -> read ~ 1/write ~ 0, dip[0] -> on ~ 1/off ~ 0
interface dip_if();
logic [3:0]dip;
modport dip_port_stim(output dip);
modport dip_port_top(input dip);
endinterface : dip_if
//interface for FRAM
// sck -> 0 ~ cummonication enabled, 1 ~ communication disabled
// clk -> system clock / timer
// miso -> testbench output
// mosi -> testbench input
interface fram_if();
logic ss;
logic mosi;
logic miso;
logic sclk;
modport fram_port_stim(input mosi, sclk, ss, output miso);
modport fram_port_top(output mosi, sclk, ss, input miso);
endinterface : fram_if
//testbenchclock replaces the oscillator on the board
interface clock_if();
logic clk;
modport clock_port_stim(output clk);
modport clock_port_top(input clk);
endinterface : clock_if

+ 92
- 0
uebung_projekt/hdl_src/sv/stimuli.sv View File

@@ -0,0 +1,92 @@
//------------------------------------------------------
//
// File : stimuli.sv
// Related Files :
// Author(s) : Mueller
// Email : muelleral82290@th-nuernberg.de
// Organization : Georg-Simon-Ohm-Hochschule Nuernberg
// Notes : Stimuli Modul
//
//------------------------------------------------------
// History
//------------------------------------------------------
// Version| Author | Mod. Date | Changes Made:
// v1.00 | Mueller | 11/05/2023 | first code
//------------------------------------------------------
//interface for LED
//reg [2:0]rbg stores rgb values that depend on dip[3:2]
//interface for DIPSCHALER
// dip[3:2] -> select colour, dip[1] -> read ~ 1/write ~ 0, dip[0] -> on ~ 1/off ~ 0
//interface for FRAM
// sck -> 0 ~ cummonication enabled, 1 ~ communication disabled
// clk -> system clock / timer
// miso -> testbench output
// mosi -> testbench input
//testbenchclock replaces the oscillator on the board
// 27.04.23 -> #delay/#oszillatordelay is not set jet
// 09.06.23 -> removed fram_if.fram_port_stim fram_spi from the stimuli parameters, moved to "fram_module"
// 09.06.23 -> oszillatordelay = 1, delay = 5
`timescale 10ns/10ps
module stimuli(led_if.led_port_stim led_stim, dip_if.dip_port_stim dip_stim, clock_if.clock_port_stim clk_stim);
// generate oszillator signal for the timer block (clock_if)
reg oszillator;
initial oszillator = 0;
always
begin
#1 oszillator <= ! oszillator;
clk_stim.clk <= ! oszillator;
end
initial
begin
/*~~~~toplevel is set to off~~~~~~~~*/
/*~~~~dip[0] is set to 0~~~~~~~~~~~~*/
dip_stim.dip = 4'b0000;
#500 dip_stim.dip = 4'b0010;
#500 dip_stim.dip = 4'b0100;
#500 dip_stim.dip = 4'b0110;
#500 dip_stim.dip = 4'b1000;
#500 dip_stim.dip = 4'b1010;
#500 dip_stim.dip = 4'b1100;
#500 dip_stim.dip = 4'b1110;
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
/*~~~~toplevel is set to on~~~~~~~~~*/
/*~~~~dip[0] is set to 1~~~~~~~~~~~~*/
/*~~fram is set to write~~~~~~~~*/
/*~~~~dip[1] is set to 0~~~~~~~~*/
#800 dip_stim.dip = 4'b0001;
#2000 dip_stim.dip = 4'b0101;
#2000 dip_stim.dip = 4'b1001;
#2000 dip_stim.dip = 4'b1101;
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
/*~~fram is set to read~~~~~~~~~*/
/*~~~~dip[1] is set to 1~~~~~~~~*/
#2000 dip_stim.dip = 4'b0011;
#2000 dip_stim.dip = 4'b0111;
#2000 dip_stim.dip = 4'b1011;
#2000 dip_stim.dip = 4'b1111;
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
end
endmodule : stimuli

+ 46
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uebung_projekt/hdl_src/sv/timer.sv View File

@@ -0,0 +1,46 @@
//------------------------------------------------------
//
// File : Timer.sv
// Related Files :
// Author(s) :
// Email :
// Organization : Georg-Simon-Ohm-Hochschule Nuernberg
// Notes :
//
//------------------------------------------------------
// History
//------------------------------------------------------
// Version| Author | Mod. Date | Changes Made:
// v1.00 | | 11.05.2023 |
//------------------------------------------------------
//eoh


module timer(bus.timer_port fpga_bus, clock_if.clock_port_top c); // (bus.timer b, clock_if.clock_port_top i)

integer counter = 0; // internal count reg
integer reload_val;

always @ (posedge c.clk or fpga_bus.dip[0]) begin
if (!fpga_bus.dip[0]) begin
counter <= 0;
fpga_bus.timer <= 0;
end else begin
if(counter <= 800) begin // zu testzwecken kürzer 1000000
counter++;
fpga_bus.timer <= 0;
end else begin
counter <= 0;
fpga_bus.timer <= 1;
end
end

end

//give the input clock on the bus
always@(posedge c.clk or negedge c.clk)
fpga_bus.clk = c.clk;

endmodule : timer


+ 99
- 0
uebung_projekt/hdl_src/sv/top_level.sv View File

@@ -0,0 +1,99 @@
// Definition of top level
module top(led_if.led_port_top l, dip_if.dip_port_top d, fram_if.fram_port_top f, clock_if.clock_port_top c);
// Initialisation of bus
bus fpga_bus();
// Initialisation of modules
timer t(fpga_bus, c);
steuerung st(fpga_bus, l);
spi s(fpga_bus, f);
parallelport p(fpga_bus, d);
endmodule : top

// Definition of bus interface
interface bus();
// bus wires
logic clk; // clock
logic timer;
logic [3:0]dip;
logic [1:0]spi_read;
// modports from modules pov
modport timer_port(input dip, output timer, clk); //dip[0]
modport parallel_port(output dip); //dip[3:0]
modport steuerung_port(input dip, timer, spi_read, clk); //dip[3:0] / spi_read[1:0]
modport spi_port(input dip, clk, timer, output spi_read); //spi_read[1:0]
endinterface : bus

// Definition of parallelport
module parallelport(bus.parallel_port b, dip_if.dip_port_top d);
//always at change of the input dip, put the change on the bus
always@(d.dip[0] or d.dip[1] or d.dip[2] or d.dip[3])
b.dip = d.dip;
endmodule

module steuerung(bus.steuerung_port b, led_if.led_port_top i);
/*...
b.dip[3:0], b.timer, b.spi_read[1:0]
i.rgb[2:0]
...*/
endmodule

/*
_______________________________________________________________________________________________________________
Testbench
__________________ ___________________
| | | |
| DIP-Schalter | | FRAM-Speicher |
| | | |
|__________________| |___________________|
| |
____________________________|________________________________________________________________|_________________
Toplevel | |
| |
dip[3:0]-->| |<--mosi, miso, sclk, ss
| |
________|_________ ________|__________
| | | |
| Parallelport | | SPI-Schnittstelle |
| | | & FRAM-Kontroller |
|__________________| |___________________|
| |
| |
dip[3:0]-->| |<--dip[3:0], timer, spi_read[1:0]
| |
| |
---------------------------------------------------------------------BUS
| |
| |
dip[0], clk, timer-->| |<--dip[3:0], timer, spi_read[1:0]
| |
________|_________ ___________________ ________|__________
| | | | | |
| Timer | | Oszillator-Takt | | Ampel-Steuerung |
| | | (auf Board) | | |
|__________________| |___________________| |___________________|
| | |
| | |
clk-->------------------------------ |<--rgb[2:0]
| |
____________________________|________________________________________________________________|___________________
| |
________|_________ ________|__________
| | | |
| Takt | | RGB-LED |
| (der Testbench) | | |
|__________________| |___________________|


__________________________________________________________________________________________________________________

*/






+ 52
- 0
uebung_projekt/hdl_src/sv/top_tb.sv View File

@@ -0,0 +1,52 @@
//------------------------------------------------------
//
// File : top.sv
// Related Files :
// Author(s) : Mueller
// Email : muelleral82290@th-nuernberg.de
// Organization : Georg-Simon-Ohm-Hochschule Nuernberg
// Notes : Stimuli Modul
//
//------------------------------------------------------
// History
//------------------------------------------------------
// Version| Author | Mod. Date | Changes Made:
// v1.00 | Mueller | 27/04/2023 | first code
//------------------------------------------------------
//eoh
//interface for LED
//reg [2:0]rbg stores rgb values that depend on dip[3:2]
//interface for DIPSCHALER
// dip[3:2] -> select colour, dip[1] -> read ~ 1/write ~ 0, dip[0] -> on ~ 1/off ~ 0
//interface for FRAM
// sck -> 0 ~ cummonication enabled, 1 ~ communication disabled
// clk -> system clock / timer
// miso -> testbench output
// mosi -> testbench input
//testbenchclock replaces the oscillator on the board
`timescale 10us/10ns
module top_tb();
// Interface
led_if stim_led_if();
dip_if stim_dip_if();
fram_if stim_fram_if();
clock_if stim_clock_if();
// Instanziierungen
top t1(stim_led_if, stim_dip_if, stim_fram_if, stim_clock_if);
stimuli s1(stim_led_if, stim_dip_if, stim_clock_if);
//fram_module f1(stim_fram_if);
// assertions
//`include "./hdl_src/sv/led_assert.txt"
endmodule : top_tb

+ 2171
- 0
uebung_projekt/modelsim.ini
File diff suppressed because it is too large
View File


+ 30
- 0
uebung_projekt/simulationsscripts/simulation.tcl View File

@@ -0,0 +1,30 @@
##------------------------------------------------------
##
## File : simulation.tcl
## Related Files :
## Author(s) : Mueller
## Email : muelleral82290@th-nuernberg.de
## Organization : Georg-Simon-Ohm-Hochschule Nuernberg
## Notes : Counter Modul
##
##------------------------------------------------------
## History
##------------------------------------------------------
## Version| Author | Mod. Date | Changes Made:
## v1.00 | Mueller | 27/04/2023 | first code
##------------------------------------------------------
quit -sim
# Aufruf der Simulation
# vsim -novopt -coverage -cvg63 -voptargs=+acc work.ShiftRegister_tb --Original
# vsim -cvg63 -voptargs=+acc work.top
vsim -cvg63 -voptargs="+acc" top_tb
do ./simulationsscripts/wave.do
# Objects im Trace-Window
# add wave sim:/top/*
# Starten des Simulators
run 210000 ns

+ 31
- 0
uebung_projekt/simulationsscripts/wave.do View File

@@ -0,0 +1,31 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -radix binary /top_tb/stim_dip_if/dip
add wave -noupdate -radix binary /top_tb/t1/fpga_bus/dip
add wave -noupdate -radix binary /top_tb/stim_clock_if/clk
add wave -noupdate -radix binary /top_tb/t1/fpga_bus/clk
add wave -noupdate -radix binary /top_tb/t1/fpga_bus/timer
add wave -noupdate -radix binary /top_tb/t1/s/FRAM_Adr
add wave -noupdate -radix binary /top_tb/t1/s/clk_cntr
add wave -noupdate -radix binary /top_tb/t1/s/FRAM_DATA_IN
add wave -noupdate -radix binary /top_tb/t1/s/FRAM_DATA_OUT
add wave -noupdate -radix binary /top_tb/t1/f/mosi
add wave -noupdate -radix binary /top_tb/t1/f/sclk
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ns} 0}
quietly wave cursor active 0
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {50 ns} {1050 ns}

+ 495
- 0
uebung_projekt/transcript View File

@@ -0,0 +1,495 @@
# // Questa Sim-64
# // Version 2019.4 linux_x86_64 Oct 15 2019
# //
# // Copyright 1991-2019 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // QuestaSim and its associated documentation contain trade
# // secrets and commercial or financial information that are the property of
# // Mentor Graphics Corporation and are privileged, confidential,
# // and exempt from disclosure under the Freedom of Information Act,
# // 5 U.S.C. Section 552. Furthermore, this information
# // is prohibited from disclosure under the Trade Secrets Act,
# // 18 U.S.C. Section 1905.
# //
do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl
#
# create workspace
# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
# vmap work ./work
# Modifying modelsim.ini
#
# Compile sv-Designfiles
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
# -- Compiling interface led_if
# -- Compiling interface dip_if
# -- Compiling interface fram_if
# -- Compiling interface clock_if
#
# Top level modules:
# --none--
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
# -- Compiling module stimuli
#
# Top level modules:
# stimuli
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
# -- Compiling module top
# -- Compiling interface bus
# -- Compiling module parallelport
# -- Compiling module steuerung
#
# Top level modules:
# top
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
# -- Compiling module top_tb
#
# Top level modules:
# top_tb
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
# -- Compiling module timer
#
# Top level modules:
# timer
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
# -- Compiling module SPI_Master
#
# Top level modules:
# SPI_Master
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
# -- Compiling module SPI_Master_With_Single_CS
#
# Top level modules:
# SPI_Master_With_Single_CS
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
# -- Compiling module FRAM
#
# Top level modules:
# FRAM
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:04:53 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
# -- Compiling module spi
#
# Top level modules:
# spi
# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
#
# Run Simulation
# vsim -cvg63 -voptargs=""+acc"" top_tb
# Start time: 14:04:53 on Jun 15,2023
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vopt-143) Recognized 1 FSM in module "SPI_Master_With_Single_CS(fast)".
# Loading sv_std.std
# Loading work.top_tb(fast)
# Loading work.led_if(fast)
# Loading work.dip_if(fast)
# Loading work.fram_if(fast)
# Loading work.clock_if(fast)
# Loading work.top(fast)
# Loading work.bus(fast)
# Loading work.timer(fast)
# Loading work.steuerung(fast)
# Loading work.spi(fast)
# Loading work.FRAM(fast)
# Loading work.SPI_Master_With_Single_CS(fast)
# Loading work.SPI_Master(fast)
# Loading work.parallelport(fast)
# Loading work.stimuli(fast)
do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl
#
# create workspace
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
# ** Warning: (vlib-34) Library already exists at "work".
# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
# vmap work ./work
# Modifying modelsim.ini
#
# Compile sv-Designfiles
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
# -- Compiling interface led_if
# -- Compiling interface dip_if
# -- Compiling interface fram_if
# -- Compiling interface clock_if
#
# Top level modules:
# --none--
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
# -- Compiling module stimuli
#
# Top level modules:
# stimuli
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
# -- Compiling module top
# -- Compiling interface bus
# -- Compiling module parallelport
# -- Compiling module steuerung
#
# Top level modules:
# top
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
# -- Compiling module top_tb
#
# Top level modules:
# top_tb
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
# -- Compiling module timer
#
# Top level modules:
# timer
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
# -- Compiling module SPI_Master
#
# Top level modules:
# SPI_Master
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
# -- Compiling module SPI_Master_With_Single_CS
#
# Top level modules:
# SPI_Master_With_Single_CS
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
# -- Compiling module FRAM
#
# Top level modules:
# FRAM
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:11:54 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
# -- Compiling module spi
#
# Top level modules:
# spi
# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
#
# Run Simulation
# End time: 14:11:55 on Jun 15,2023, Elapsed time: 0:07:02
# Errors: 12, Warnings: 1
# vsim -cvg63 -voptargs=""+acc"" top_tb
# Start time: 14:11:55 on Jun 15,2023
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading sv_std.std
# Loading work.top_tb(fast)
# Loading work.led_if(fast)
# Loading work.dip_if(fast)
# Loading work.fram_if(fast)
# Loading work.clock_if(fast)
# Loading work.top(fast)
# Loading work.bus(fast)
# Loading work.timer(fast)
# Loading work.steuerung(fast)
# Loading work.spi(fast)
# Loading work.FRAM(fast)
# Loading work.SPI_Master_With_Single_CS(fast)
# Loading work.SPI_Master(fast)
# Loading work.parallelport(fast)
# Loading work.stimuli(fast)
# Can't move the Now cursor.
# Can't move the Now cursor.
add wave -position insertpoint \
sim:/top_tb/t1/f/mosi
do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl
#
# create workspace
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
# ** Warning: (vlib-34) Library already exists at "work".
# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
# vmap work ./work
# Modifying modelsim.ini
#
# Compile sv-Designfiles
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:00 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
# -- Compiling interface led_if
# -- Compiling interface dip_if
# -- Compiling interface fram_if
# -- Compiling interface clock_if
#
# Top level modules:
# --none--
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:00 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
# -- Compiling module stimuli
#
# Top level modules:
# stimuli
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:00 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
# -- Compiling module top
# -- Compiling interface bus
# -- Compiling module parallelport
# -- Compiling module steuerung
#
# Top level modules:
# top
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:00 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
# -- Compiling module top_tb
#
# Top level modules:
# top_tb
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:00 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
# -- Compiling module timer
#
# Top level modules:
# timer
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:01 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
# -- Compiling module SPI_Master
#
# Top level modules:
# SPI_Master
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:01 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
# -- Compiling module SPI_Master_With_Single_CS
#
# Top level modules:
# SPI_Master_With_Single_CS
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:01 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
# -- Compiling module FRAM
#
# Top level modules:
# FRAM
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:19:01 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
# -- Compiling module spi
#
# Top level modules:
# spi
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
#
# Run Simulation
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:07:06
# Errors: 12, Warnings: 1
# vsim -cvg63 -voptargs=""+acc"" top_tb
# Start time: 14:19:01 on Jun 15,2023
# ** Note: (vsim-8009) Loading existing optimized design _opt
# Loading sv_std.std
# Loading work.top_tb(fast)
# Loading work.led_if(fast)
# Loading work.dip_if(fast)
# Loading work.fram_if(fast)
# Loading work.clock_if(fast)
# Loading work.top(fast)
# Loading work.bus(fast)
# Loading work.timer(fast)
# Loading work.steuerung(fast)
# Loading work.spi(fast)
# Loading work.FRAM(fast)
# Loading work.SPI_Master_With_Single_CS(fast)
# Loading work.SPI_Master(fast)
# Loading work.parallelport(fast)
# Loading work.stimuli(fast)
do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl
#
# create workspace
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
# ** Warning: (vlib-34) Library already exists at "work".
# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
# vmap work ./work
# Modifying modelsim.ini
#
# Compile sv-Designfiles
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
# -- Compiling interface led_if
# -- Compiling interface dip_if
# -- Compiling interface fram_if
# -- Compiling interface clock_if
#
# Top level modules:
# --none--
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
# -- Compiling module stimuli
#
# Top level modules:
# stimuli
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
# -- Compiling module top
# -- Compiling interface bus
# -- Compiling module parallelport
# -- Compiling module steuerung
#
# Top level modules:
# top
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
# -- Compiling module top_tb
#
# Top level modules:
# top_tb
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
# -- Compiling module timer
#
# Top level modules:
# timer
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
# -- Compiling module SPI_Master
#
# Top level modules:
# SPI_Master
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
# -- Compiling module SPI_Master_With_Single_CS
#
# Top level modules:
# SPI_Master_With_Single_CS
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:07 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
# -- Compiling module FRAM
#
# Top level modules:
# FRAM
# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
# Start time: 14:22:08 on Jun 15,2023
# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
# -- Compiling module spi
#
# Top level modules:
# spi
# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
#
# Run Simulation
# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:03:07
# Errors: 5, Warnings: 1
# vsim -cvg63 -voptargs=""+acc"" top_tb
# Start time: 14:22:08 on Jun 15,2023
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading sv_std.std
# Loading work.top_tb(fast)
# Loading work.led_if(fast)
# Loading work.dip_if(fast)
# Loading work.fram_if(fast)
# Loading work.clock_if(fast)
# Loading work.top(fast)
# Loading work.bus(fast)
# Loading work.timer(fast)
# Loading work.steuerung(fast)
# Loading work.spi(fast)
# Loading work.FRAM(fast)
# Loading work.SPI_Master_With_Single_CS(fast)
# Loading work.SPI_Master(fast)
# Loading work.parallelport(fast)
# Loading work.stimuli(fast)

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R9
r1
!s85 0
31
!s108 1686831728.000000
!s107 ./hdl_src/sv/fram.sv|
!s90 -reportprogress|300|-work|work|./hdl_src/sv/fram.sv|
!i113 0
R13
R2
vSPI_Master
R3
R4
!i10b 1
!s100 LNaIK]EJb:HMhCL_bcUOT2
!s11b RZ[UYHW;Fa4LhmckzB[<X2
IFYo`G3DmU9[M^WeGMdfi73
R5
S1
R0
w1686826806
8./hdl_src/sv/SPI_Master_Control.sv
F./hdl_src/sv/SPI_Master_Control.sv
!i122 -1
Z19 L0 34
R9
r1
!s85 0
31
R10
!s107 ./hdl_src/sv/SPI_Master_Control.sv|
!s90 -reportprogress|300|-work|work|./hdl_src/sv/SPI_Master_Control.sv|
!i113 0
R13
R2
n@s@p@i_@master
vSPI_Master_With_Single_CS
R3
R4
!i10b 1
!s100 15??SlXF;4=1UHZHFcb4D2
!s11b iXFhD1[A]RQ:BgzgT;=fY3
ID5Z=T=j@LdzO_?_@1UFZC3
R5
S1
R0
w1686826875
8./hdl_src/sv/SPI_Master.sv
F./hdl_src/sv/SPI_Master.sv
!i122 -1
Z20 L0 38
R9
r1
!s85 0
31
R10
!s107 ./hdl_src/sv/SPI_Master.sv|
!s90 -reportprogress|300|-work|work|./hdl_src/sv/SPI_Master.sv|
!i113 0
R13
R2
n@s@p@i_@master_@with_@single_@c@s
vsteuerung
R3
R4
!i10b 1
!s100 >DGbebG_Mk0W]hI8XCQ?k0
!s11b WKleG=JcKL4FgO@TP[IO[1
IE`WCa5G2QlghM9EX[<1dS3
R5
S1
R0
R6
R7
R8
!i122 -1
R20
R9
r1
!s85 0
31
R10
R11
R12
!i113 0
R13
R2
vstimuli
R3
R4
!i10b 1
!s100 ?c<R_8azXOe4?MR6PN9lb1
!s11b f7UOC6iFO:78SRcz4Ojgc1
IFCieJ4l88EVc2aVF84efc1
R5
S1
R0
w1686831722
8./hdl_src/sv/stimuli.sv
F./hdl_src/sv/stimuli.sv
!i122 -1
L0 37
R9
r1
!s85 0
31
R10
!s107 ./hdl_src/sv/stimuli.sv|
!s90 -reportprogress|300|-work|work|./hdl_src/sv/stimuli.sv|
!i113 0
R13
R2
vtimer
R3
R4
!i10b 1
!s100 ^LgdMGMo^z_E<7OKUmDz:0
!s11b [5XV:J9W^QFe>5GG;9B8k3
IEenLI0W00diXD61Ele2;U0
R5
S1
R0
w1686831703
8./hdl_src/sv/timer.sv
F./hdl_src/sv/timer.sv
!i122 -1
L0 19
R9
r1
!s85 0
31
R10
!s107 ./hdl_src/sv/timer.sv|
!s90 -reportprogress|300|-work|work|./hdl_src/sv/timer.sv|
!i113 0
R13
R2
vtop
R3
R4
!i10b 1
!s100 6?3aiGY1NTOnA[jU;ZnEa3
!s11b =zPVnM;Zm1L1Ig2finB;E2
I^g60QFGiK:2<OB;dYJIk23
R5
S1
R0
R6
R7
R8
!i122 -1
L0 2
R9
r1
!s85 0
31
R10
R11
R12
!i113 0
R13
R2
vtop_tb
R3
R4
!i10b 1
!s100 MLz@z6Rj=WV;42>b=KZhX2
!s11b jcE]a:O3cJ<=CdGZ:MgQ62
IbRb[2DAWSb2IUOHB[hFz:2
R5
S1
R0
w1686315659
8./hdl_src/sv/top_tb.sv
F./hdl_src/sv/top_tb.sv
!i122 -1
R19
R9
r1
!s85 0
31
R10
!s107 ./hdl_src/sv/top_tb.sv|
!s90 -reportprogress|300|-work|work|./hdl_src/sv/top_tb.sv|
!i113 0
R13
R2

BIN
uebung_projekt/work/_lib.qdb View File


BIN
uebung_projekt/work/_lib1_0.qdb View File


+ 0
- 0
uebung_projekt/work/_lib1_0.qpg View File


BIN
uebung_projekt/work/_lib1_0.qtl View File


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uebung_projekt/work/_opt__lock View File

@@ -0,0 +1 @@
muelleral82290@efiapps1.efi.fh-nuernberg.de, pid = 21917

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uebung_projekt/work/_vmake View File

@@ -0,0 +1,4 @@
m255
K4
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cModel Technology

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