uebung_projekt

2023-06-15 14:35:20 +02:00
parent d8f3dff5cf
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+## -------------------------------------------------------------
+##                                                                       
+##  File          :  compile.tcl    
+##  Author(s)     :  Baesig      
+##					 Gerstner                                       
+##  Email         :  juergen.baesig@fh-nuernberg.de 
+##					 Gerstnermi46611@th-nuernberg.de                    
+##  Organization  :  Georg-Simon-Ohm-Hochschule Nuernberg                      
+##                             
+##  Note          :   
+##         
+## -------------------------------------------------------------
+##                                 History    
+## -------------------------------------------------------------
+##    Version| Author   | Mod. Date  | Changes Made:
+##    v1.00  | Baesig   | 09/04/2012 | first code
+##    v1.01  | Gerstner | 20/09/2013 | modified
+## -------------------------------------------------------------
+##eoh
+
+.main clear
+
+echo
+# ----------------------------------------------------------
+echo "create workspace"
+ if [file exists work] { vdel -all }
+ vlib work
+ vmap work ./work
+echo
+# ----------------------------------------------------------
+echo " Compile sv-Designfiles "
+vlog -work work ./hdl_src/sv/interface.sv
+vlog -work work ./hdl_src/sv/stimuli.sv
+vlog -work work ./hdl_src/sv/top_level.sv
+vlog -work work ./hdl_src/sv/top_tb.sv
+vlog -work work ./hdl_src/sv/timer.sv
+vlog -work work ./hdl_src/sv/SPI_Master_Control.sv
+vlog -work work ./hdl_src/sv/SPI_Master.sv
+vlog -work work ./hdl_src/sv/FRAM_Controller.sv
+vlog -work work ./hdl_src/sv/fram.sv
+
+echo
+# ----------------------------------------------------------
+echo " Run Simulation "
+source ./simulationsscripts/simulation.tcl
+