Lösung des Praktikums Systementwurf
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

test_task_sine.vhd 4.2KB

1 year ago
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. use ieee.float_pkg.all;
  5. library work;
  6. use work.reg32.all;
  7. use work.avalon_slave.all;
  8. use work.test_utility.all;
  9. use work.test_avalon_slave.all;
  10. use work.task.all;
  11. use work.sine_data.all;
  12. use work.test_hardware_task.all;
  13. use work.test_data_channel_pkg.all;
  14. library std;
  15. use std.env.all;
  16. use std.textio.all;
  17. entity test_task_sine is
  18. generic( CHECK_RESULTS : boolean; GUI_MODE : boolean := false );
  19. end entity test_task_sine;
  20. architecture test of test_task_sine is
  21. procedure test_configure( signal clk : in std_logic;
  22. signal req : out work.avalon_slave.Request;
  23. signal rsp : in work.avalon_slave.Response ) is
  24. variable index : integer := 0;
  25. variable writedata : std_logic_vector( 31 downto 0 );
  26. begin
  27. std.textio.write( std.textio.OUTPUT, " test_configure ... " );
  28. index := 0;
  29. writedata := x"08000000"; -- 2^32 / 32
  30. write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
  31. index => index, config => writedata );
  32. index := 1;
  33. writedata := x"00000000";
  34. write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
  35. index => index, config => writedata );
  36. index := 2;
  37. writedata := x"40800000"; -- 2 ** 2 = 4 float
  38. write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
  39. index => index, config => writedata );
  40. std.textio.write( std.textio.OUTPUT, TEST_OK );
  41. end procedure test_configure;
  42. signal clk : std_logic := '0';
  43. signal reset : std_logic := '1';
  44. signal req : work.avalon_slave.Request;
  45. signal rsp : work.avalon_slave.Response;
  46. signal data_channel_req : work.avalon_slave.Request;
  47. signal data_channel_rsp : work.avalon_slave.Response;
  48. signal signal_write : std_logic;
  49. signal signal_writedata : std_logic_vector( 31 downto 0 );
  50. signal data_channel_read : std_logic;
  51. signal data_channel_readdata : std_logic_vector( 31 downto 0 );
  52. begin
  53. dut : entity work.task_sine
  54. port map (
  55. clk => clk,
  56. reset => reset,
  57. address => req.address,
  58. read => req.read,
  59. readdata => rsp.readdata,
  60. write => req.write,
  61. writedata => req.writedata,
  62. signal_write => signal_write,
  63. signal_writedata => signal_writedata
  64. );
  65. u_data_channel : entity work.data_channel
  66. port map (
  67. clk => clk,
  68. reset => reset,
  69. ctrl_address => data_channel_req.address,
  70. ctrl_read => data_channel_req.read,
  71. ctrl_readdata => data_channel_rsp.readdata,
  72. ctrl_write => data_channel_req.write,
  73. ctrl_writedata => data_channel_req.writedata,
  74. hw_sink_write => signal_write,
  75. hw_sink_writedata => signal_writedata,
  76. hw_source_read => data_channel_read,
  77. hw_source_readdata => data_channel_readdata
  78. );
  79. clk <= not clk after 10 ns;
  80. reset_release : process
  81. begin
  82. wait for 35 ns;
  83. reset <= '0';
  84. wait;
  85. end process reset_release;
  86. stimulus : process
  87. variable data_channel_config : std_logic_vector( 31 downto 0 ) := x"00000001";
  88. begin
  89. wait until falling_edge( reset );
  90. work.test_data_channel_pkg.write_and_assert_config( clk => clk,
  91. req => data_channel_req,
  92. rsp => data_channel_rsp,
  93. config => data_channel_config );
  94. test_configure( clk => clk, req => req, rsp => rsp );
  95. test_execute( clk => clk, req => req, rsp => rsp,
  96. write => signal_write, writedata => signal_writedata );
  97. if ( CHECK_RESULTS ) then
  98. check_and_write_content( clk => clk,
  99. req => data_channel_req, rsp => data_channel_rsp,
  100. expected => work.sine_data.expected );
  101. else
  102. write_content( clk => clk,
  103. req => data_channel_req, rsp => data_channel_rsp );
  104. end if;
  105. if ( GUI_MODE ) then
  106. std.env.stop;
  107. else
  108. std.env.finish;
  109. end if;
  110. end process stimulus;
  111. end architecture test;