Lösung des Praktikums Systementwurf
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hardware_task_hw.tcl 5.0KB

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  1. # TCL File Generated by Component Editor 21.1
  2. # Thu Sep 08 23:38:44 CEST 2022
  3. # DO NOT MODIFY
  4. #
  5. # hardware_task "hardware_task" v1.0
  6. # 2022.09.08.23:38:44
  7. # A hardware task status and control interface
  8. #
  9. #
  10. # request TCL package from ACDS 16.1
  11. #
  12. package require -exact qsys 16.1
  13. #
  14. # module hardware_task
  15. #
  16. set_module_property DESCRIPTION "A hardware task status and control interface"
  17. set_module_property NAME hardware_task
  18. set_module_property VERSION 1.0
  19. set_module_property INTERNAL false
  20. set_module_property OPAQUE_ADDRESS_MAP true
  21. set_module_property GROUP signal_processing
  22. set_module_property AUTHOR ""
  23. set_module_property DISPLAY_NAME hardware_task
  24. set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
  25. set_module_property EDITABLE true
  26. set_module_property REPORT_TO_TALKBACK false
  27. set_module_property ALLOW_GREYBOX_GENERATION false
  28. set_module_property REPORT_HIERARCHY false
  29. #
  30. # file sets
  31. #
  32. add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
  33. set_fileset_property QUARTUS_SYNTH TOP_LEVEL hardware_task
  34. set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
  35. set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
  36. add_fileset_file hardware_task.vhd VHDL PATH hardware/system/hardware_task.vhd TOP_LEVEL_FILE
  37. #
  38. # parameters
  39. #
  40. #
  41. # display items
  42. #
  43. #
  44. # connection point reset
  45. #
  46. add_interface reset reset end
  47. set_interface_property reset associatedClock clock
  48. set_interface_property reset synchronousEdges DEASSERT
  49. set_interface_property reset ENABLED true
  50. set_interface_property reset EXPORT_OF ""
  51. set_interface_property reset PORT_NAME_MAP ""
  52. set_interface_property reset CMSIS_SVD_VARIABLES ""
  53. set_interface_property reset SVD_ADDRESS_GROUP ""
  54. add_interface_port reset reset reset Input 1
  55. #
  56. # connection point ctrl
  57. #
  58. add_interface ctrl avalon end
  59. set_interface_property ctrl addressUnits WORDS
  60. set_interface_property ctrl associatedClock clock
  61. set_interface_property ctrl associatedReset reset
  62. set_interface_property ctrl bitsPerSymbol 8
  63. set_interface_property ctrl burstOnBurstBoundariesOnly false
  64. set_interface_property ctrl burstcountUnits WORDS
  65. set_interface_property ctrl explicitAddressSpan 0
  66. set_interface_property ctrl holdTime 0
  67. set_interface_property ctrl linewrapBursts false
  68. set_interface_property ctrl maximumPendingReadTransactions 0
  69. set_interface_property ctrl maximumPendingWriteTransactions 0
  70. set_interface_property ctrl readLatency 0
  71. set_interface_property ctrl readWaitTime 1
  72. set_interface_property ctrl setupTime 0
  73. set_interface_property ctrl timingUnits Cycles
  74. set_interface_property ctrl writeWaitTime 0
  75. set_interface_property ctrl ENABLED true
  76. set_interface_property ctrl EXPORT_OF ""
  77. set_interface_property ctrl PORT_NAME_MAP ""
  78. set_interface_property ctrl CMSIS_SVD_VARIABLES ""
  79. set_interface_property ctrl SVD_ADDRESS_GROUP ""
  80. add_interface_port ctrl ctrl_address address Input 4
  81. add_interface_port ctrl ctrl_read read Input 1
  82. add_interface_port ctrl ctrl_readdata readdata Output 32
  83. add_interface_port ctrl ctrl_write write Input 1
  84. add_interface_port ctrl ctrl_writedata writedata Input 32
  85. set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
  86. set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
  87. set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
  88. set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0
  89. #
  90. # connection point task
  91. #
  92. add_interface task avalon start
  93. set_interface_property task addressUnits SYMBOLS
  94. set_interface_property task associatedClock clock
  95. set_interface_property task associatedReset reset
  96. set_interface_property task bitsPerSymbol 8
  97. set_interface_property task burstOnBurstBoundariesOnly false
  98. set_interface_property task burstcountUnits WORDS
  99. set_interface_property task doStreamReads false
  100. set_interface_property task doStreamWrites false
  101. set_interface_property task holdTime 0
  102. set_interface_property task linewrapBursts false
  103. set_interface_property task maximumPendingReadTransactions 0
  104. set_interface_property task maximumPendingWriteTransactions 0
  105. set_interface_property task readLatency 0
  106. set_interface_property task readWaitTime 1
  107. set_interface_property task setupTime 0
  108. set_interface_property task timingUnits Cycles
  109. set_interface_property task writeWaitTime 0
  110. set_interface_property task ENABLED true
  111. set_interface_property task EXPORT_OF ""
  112. set_interface_property task PORT_NAME_MAP ""
  113. set_interface_property task CMSIS_SVD_VARIABLES ""
  114. set_interface_property task SVD_ADDRESS_GROUP ""
  115. add_interface_port task task_address address Output 4
  116. add_interface_port task task_read read Output 1
  117. add_interface_port task task_readdata readdata Input 32
  118. add_interface_port task task_write write Output 1
  119. add_interface_port task task_writedata writedata Output 32
  120. #
  121. # connection point clock
  122. #
  123. add_interface clock clock end
  124. set_interface_property clock clockRate 0
  125. set_interface_property clock ENABLED true
  126. set_interface_property clock EXPORT_OF ""
  127. set_interface_property clock PORT_NAME_MAP ""
  128. set_interface_property clock CMSIS_SVD_VARIABLES ""
  129. set_interface_property clock SVD_ADDRESS_GROUP ""
  130. add_interface_port clock clk clk Input 1