80 lines
2.7 KiB
Plaintext
80 lines
2.7 KiB
Plaintext
# OpenFile ./cpu_tb.sv
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ls
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# alu_tb.sv decoder_tb.sv pc_tb.sv transcript
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# cpu_tb.sv main_mem_tb.sv reg_file_tb.sv work
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vsim compile.tcl
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# vsim compile.tcl
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# Start time: 11:01:25 on Nov 28,2025
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# ** Error (suppressible): (vsim-19) Failed to access library 'compile' at "compile".
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# No such file or directory. (errno = ENOENT)
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# Error loading design
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# End time: 11:01:25 on Nov 28,2025, Elapsed time: 0:00:00
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# Errors: 1, Warnings: 0
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ls
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# alu_tb.sv decoder_tb.sv pc_tb.sv transcript
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# cpu_tb.sv main_mem_tb.sv reg_file_tb.sv work
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cd ..
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ls
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# rtl verilator wave_configs
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cd ..
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pwd
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# C:/PhD/RISC-V Design Course Material/RISC-V Desgin Course - Complete Source Code/riscv_in3days-public/hw
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cd ..
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ls
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# README.md doc hw sw
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cd ..
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ls
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# riscv_in3days-public
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cd ..
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ls
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# Course Introduction & Closing - Public.pdf
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# Day 1
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# Day 2
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# Day 3
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# Day 4
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# RISC-V Desgin Course - Complete Source Code
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# References
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cd ..
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cd ..
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la
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# ambiguous command name "la": label labelframe langOf lappend lassign lattice_edition layout
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ls
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# Drivers Program Files (x86) inetpub
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# DumpStack.log Steam_Community_Markt intelFPGA
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# Lukas Users intelFPGA_lite
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# PhD Windows vfcompat.dll
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# ProcLogs appverifUI.dll
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# Program Files flexlm
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pwd
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# C:/
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ls
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# Drivers Program Files (x86) inetpub
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# DumpStack.log Steam_Community_Markt intelFPGA
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# Lukas Users intelFPGA_lite
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# PhD Windows vfcompat.dll
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# ProcLogs appverifUI.dll
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# Program Files flexlm
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cd PhD
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ls
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# Code compile.tcl
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# RISC-V Design Course Material
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cd RISC-V Design Course Material
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# wrong # args: should be "cd ?dirName?"
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ls
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# Code compile.tcl
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# RISC-V Design Course Material
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ls
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# Code compile.tcl
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# RISC-V Design Course Material
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cd RISC-V Design Course Material
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# wrong # args: should be "cd ?dirName?"
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ls
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# Code compile.tcl
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# RISC-V Design Course Material
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run compile.tcl
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# No Design Loaded!
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compile.tcl
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# couldn't execute ".\compile.tcl": no such file or directory
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run compile.tcl
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# No Design Loaded!
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