38 lines
1.4 KiB
Systemverilog
38 lines
1.4 KiB
Systemverilog
// *********************************************************************************************
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 12.Jun.2025 by Lund University [commit 5b1e415]
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// Last Modified : 23.Oct.2025 by Bomin Kim [commit 2f8f03d]
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// -----
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// HISTORY : Date By Comments
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// ----------- --------- -------------------------------------------------
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// 15.Oct.2025 Bomin Kim Moved NextPC logic from decoder into PC
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// 15.Oct.2025 Bomin Kim Removed reset condition from combinational logic
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// *********************************************************************************************
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module pc (
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output logic[31:0] CurrentPC,
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input logic[31:0] JumpOrBranchPC,
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input logic JumpOrBranch,
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output logic[31:0] NextPC,
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input logic reset,
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input logic clk
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);
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// NextPC logic; next-state function
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always_comb begin : Next_PC
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if (JumpOrBranch) NextPC = JumpOrBranchPC;
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else NextPC = CurrentPC + 4;
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end
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// CurrentPC logic; state register
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always_ff @(posedge clk) begin
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if (reset) CurrentPC <= '0;
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else CurrentPC <= NextPC;
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end
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endmodule
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