90 lines
2.7 KiB
VHDL
90 lines
2.7 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.reg32.all;
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use work.avalon_slave.all;
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package test_avalon_slave is
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procedure read( signal clk : in std_logic;
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variable address : in std_logic_vector;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable data : out std_logic_vector );
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procedure assert_readdata_eq( signal clk : in std_logic;
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variable address : in std_logic_vector;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable expected : in std_logic_vector;
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constant message : in string );
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procedure write( signal clk : in std_logic;
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variable address : in std_logic_vector;
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signal req : out work.avalon_slave.Request;
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variable data : in std_logic_vector );
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end package test_avalon_slave;
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package body test_avalon_slave is
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procedure read( signal clk : in std_logic;
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variable address : in std_logic_vector;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable data : out std_logic_vector ) is
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begin
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req.read <= '1';
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req.write <= '0';
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req.address <= address;
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wait until falling_edge( clk );
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wait until falling_edge( clk );
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req.read <= '0';
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data := rsp.readdata;
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wait until falling_edge( clk );
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end procedure read;
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procedure assert_readdata_eq( signal clk : in std_logic;
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variable address : in std_logic_vector;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable expected :in std_logic_vector;
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constant message : in string ) is
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variable readdata : std_logic_vector( expected'range );
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begin
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read( clk => clk,
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address => address,
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req => req,
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rsp => rsp,
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data => readdata );
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assert( readdata = expected )
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report message & LF &
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" expected: " & to_string( expected ) & LF &
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" actual: " & to_string( readdata ) & LF
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severity error;
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end procedure assert_readdata_eq;
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procedure write( signal clk : in std_logic;
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variable address : in std_logic_vector;
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signal req : out work.avalon_slave.Request;
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variable data : in std_logic_vector ) is
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begin
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req.read <= '0';
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req.write <= '1';
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req.address <= address;
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req.writedata <= data;
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wait until falling_edge( clk );
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req.write <= '0';
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end procedure write;
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end package body test_avalon_slave;
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