437 lines
16 KiB
VHDL
437 lines
16 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.float_pkg.all;
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library work;
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use work.avalon_slave.all;
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use work.test_utility.all;
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library std;
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use std.textio.all;
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package test_data_channel_pkg is
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procedure is_empty( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable res : out boolean );
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procedure assert_empty( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response );
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procedure assert_not_empty( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response );
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procedure assert_full( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response );
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procedure assert_not_full( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response );
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procedure assert_level( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable level : in std_logic_vector );
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procedure assert_config( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable config : in std_logic_vector );
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procedure write_config( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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variable config : in std_logic_vector );
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procedure write_and_assert_config( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable config : in std_logic_vector );
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procedure write_clear( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request );
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procedure write_sw_sink( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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variable data : in std_logic_vector );
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procedure read_sw_source( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable data : out std_logic_vector );
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procedure assert_read_sw_source_eq( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable expected : in std_logic_vector );
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procedure write_hw_sink( signal clk : in std_logic;
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signal write : out std_logic;
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signal writedata : out std_logic_vector;
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variable data : in std_logic_vector );
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procedure assert_read_hw_source_eq( signal clk : in std_logic;
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signal read : out std_logic;
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signal readdata : in std_logic_vector;
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variable expected : in std_logic_vector );
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procedure write_content( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response );
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procedure check_and_write_content( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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constant expected : real_array );
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end package test_data_channel_pkg;
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package body test_data_channel_pkg is
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procedure is_empty( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable res : out boolean ) is
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variable address : std_logic_vector( 3 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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constant EMPTY : std_logic_vector( 31 downto 0 ) := x"00000001";
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 1, address'length ) );
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work.test_avalon_slave.read( clk => clk,
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address => address,
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req => req,
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rsp => rsp,
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data => data );
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res := data = EMPTY;
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end procedure is_empty;
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procedure assert_empty( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response ) is
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variable address : std_logic_vector( 3 downto 0 );
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variable expected_readdata : std_logic_vector( 31 downto 0 ) := x"00000001";
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 1, address'length ) );
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expected_readdata := x"00000001";
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work.test_avalon_slave.assert_readdata_eq( clk => clk,
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address => address,
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req => req,
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rsp => rsp,
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expected => expected_readdata,
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message => TEST_FAIL & " assert_empty" );
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end procedure assert_empty;
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procedure assert_not_empty( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response ) is
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variable address : std_logic_vector( 3 downto 0 );
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variable expected_readdata : std_logic_vector( 31 downto 0 ) := x"00000001";
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 1, address'length ) );
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expected_readdata := x"00000000";
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work.test_avalon_slave.assert_readdata_eq( clk => clk,
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address => address,
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req => req,
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rsp => rsp,
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expected => expected_readdata,
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message => TEST_FAIL & " assert_not_empty" );
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end procedure assert_not_empty;
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procedure assert_full( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response ) is
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variable address : std_logic_vector( 3 downto 0 );
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variable expected_readdata : std_logic_vector( 31 downto 0 ) := x"00000001";
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 2, address'length ) );
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expected_readdata := x"00000001";
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work.test_avalon_slave.assert_readdata_eq( clk => clk,
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address => address,
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req => req,
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rsp => rsp,
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expected => expected_readdata,
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message => TEST_FAIL & " assert_full" );
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end procedure assert_full;
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procedure assert_not_full( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response ) is
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variable address : std_logic_vector( 3 downto 0 );
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variable expected_readdata : std_logic_vector( 31 downto 0 ) := x"00000001";
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 2, address'length ) );
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expected_readdata := x"00000000";
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work.test_avalon_slave.assert_readdata_eq( clk => clk,
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address => address,
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req => req,
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rsp => rsp,
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expected => expected_readdata,
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message => TEST_FAIL & " assert_not_full" );
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end procedure assert_not_full;
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procedure assert_level( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable level : in std_logic_vector ) is
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variable address : std_logic_vector( 3 downto 0 );
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 3, address'length ) );
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work.test_avalon_slave.assert_readdata_eq( clk => clk,
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address => address,
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req => req,
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rsp => rsp,
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expected => level,
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message => TEST_FAIL & " assert_level" );
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end procedure assert_level;
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procedure assert_config( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable config : in std_logic_vector ) is
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variable address : std_logic_vector( 3 downto 0 );
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 0, address'length ) );
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work.test_avalon_slave.assert_readdata_eq( clk => clk,
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address => address,
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req => req,
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rsp => rsp,
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expected => config,
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message => TEST_FAIL & " assert_config" );
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end procedure assert_config;
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procedure write_config( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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variable config : in std_logic_vector ) is
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variable address : std_logic_vector( 3 downto 0 );
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 0, address'length ) );
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work.test_avalon_slave.write( clk => clk,
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address => address,
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req => req,
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data => config );
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end procedure write_config;
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procedure write_and_assert_config( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable config : in std_logic_vector ) is
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variable address : std_logic_vector( 3 downto 0 );
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begin
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write_config( clk => clk, req => req, config => config );
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assert_config( clk => clk, req => req, rsp => rsp, config => config );
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end procedure write_and_assert_config;
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procedure write_clear( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request ) is
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variable address : std_logic_vector( 3 downto 0 );
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variable clear : std_logic_vector( 31 downto 0 ) := x"00000001";
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 6, address'length ) );
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work.test_avalon_slave.write( clk => clk,
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address => address,
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req => req,
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data => clear );
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end procedure write_clear;
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procedure write_sw_sink( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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variable data : in std_logic_vector ) is
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variable address : std_logic_vector( 3 downto 0 );
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 4, address'length ) );
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work.test_avalon_slave.write( clk => clk,
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address => address,
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req => req,
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data => data );
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end procedure write_sw_sink;
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procedure read_sw_source( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable data : out std_logic_vector ) is
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variable address : std_logic_vector( 3 downto 0 );
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 5, address'length ) );
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work.test_avalon_slave.read( clk => clk,
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address => address,
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req => req,
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rsp => rsp,
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data => data );
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end procedure read_sw_source;
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procedure assert_read_sw_source_eq( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable expected : in std_logic_vector ) is
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variable address : std_logic_vector( 3 downto 0 );
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 5, address'length ) );
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work.test_avalon_slave.assert_readdata_eq( clk => clk,
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address => address,
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req => req,
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rsp => rsp,
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expected => expected,
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message => TEST_FAIL & " assert_readdata_eq" );
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end procedure assert_read_sw_source_eq;
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procedure write_hw_sink( signal clk : in std_logic;
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signal write : out std_logic;
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signal writedata : out std_logic_vector;
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variable data : in std_logic_vector ) is
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begin
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wait until falling_edge( clk );
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write <= '1';
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writedata <= data;
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wait until falling_edge( clk );
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write <= '0';
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end procedure write_hw_sink;
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procedure assert_read_hw_source_eq( signal clk : in std_logic;
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signal read : out std_logic;
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signal readdata : in std_logic_vector;
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variable expected : in std_logic_vector ) is
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begin
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wait until falling_edge( clk );
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assert( readdata = expected )
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report TEST_FAIL & " assert_read_hw_source_eq" & LF &
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" expected: " & to_string( expected ) & LF &
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" actual: " & to_string( readdata ) & LF
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severity error;
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wait until falling_edge( clk );
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read <= '1';
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wait until falling_edge( clk );
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read <= '0';
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end procedure assert_read_hw_source_eq;
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procedure write_content( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response ) is
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variable index : integer := 0;
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variable empty : boolean;
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variable value : std_logic_vector( 31 downto 0 );
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variable float_value : float32;
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variable real_value : real;
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file data_file : text;
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begin
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std.textio.write( std.textio.OUTPUT, " write_content ... " );
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file_open( data_file, "data.py", write_mode );
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std.textio.write( data_file, "float_data = [" );
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while true loop
|
||
|
|
is_empty( clk => clk, req => req, rsp => rsp, res => empty );
|
||
|
|
if ( empty ) then
|
||
|
|
exit;
|
||
|
|
end if;
|
||
|
|
read_sw_source( clk => clk, req => req, rsp => rsp,
|
||
|
|
data => value );
|
||
|
|
float_value := to_float( value );
|
||
|
|
real_value := to_real( float_value );
|
||
|
|
std.textio.write( data_file, to_string( real_value ) & "," );
|
||
|
|
index := index + 1;
|
||
|
|
end loop;
|
||
|
|
|
||
|
|
while index < 1024 loop
|
||
|
|
std.textio.write( data_file, "0.0 ," );
|
||
|
|
index := index + 1;
|
||
|
|
end loop;
|
||
|
|
|
||
|
|
std.textio.write( data_file, "]" & LF );
|
||
|
|
file_close( data_file );
|
||
|
|
|
||
|
|
std.textio.write( std.textio.OUTPUT, TEST_OK );
|
||
|
|
end procedure write_content;
|
||
|
|
|
||
|
|
procedure check_and_write_content( signal clk : in std_logic;
|
||
|
|
signal req : out work.avalon_slave.Request;
|
||
|
|
signal rsp : in work.avalon_slave.Response;
|
||
|
|
constant expected : real_array ) is
|
||
|
|
|
||
|
|
variable expected_readdata : std_logic_vector( 31 downto 0 );
|
||
|
|
variable index : integer := 0;
|
||
|
|
variable empty : boolean;
|
||
|
|
variable value : std_logic_vector( 31 downto 0 );
|
||
|
|
variable float_value : float32;
|
||
|
|
variable real_value : real;
|
||
|
|
variable expected_value : real;
|
||
|
|
variable abs_err : real := 0.5e-1;
|
||
|
|
file data_file : text;
|
||
|
|
begin
|
||
|
|
std.textio.write( std.textio.OUTPUT, " check_and_write_content ... " );
|
||
|
|
|
||
|
|
assert_full( clk => clk, req => req, rsp => rsp );
|
||
|
|
|
||
|
|
expected_readdata := std_logic_vector( to_unsigned( 0, expected_readdata'length ) );
|
||
|
|
assert_level( clk => clk, req => req, rsp => rsp,
|
||
|
|
level => expected_readdata );
|
||
|
|
|
||
|
|
file_open( data_file, "data.py", write_mode );
|
||
|
|
std.textio.write( data_file, "float_data = [" );
|
||
|
|
|
||
|
|
while true loop
|
||
|
|
is_empty( clk => clk, req => req, rsp => rsp, res => empty );
|
||
|
|
if ( empty ) then
|
||
|
|
exit;
|
||
|
|
end if;
|
||
|
|
read_sw_source( clk => clk, req => req, rsp => rsp,
|
||
|
|
data => value );
|
||
|
|
float_value := to_float( value );
|
||
|
|
real_value := to_real( float_value );
|
||
|
|
std.textio.write( data_file, to_string( real_value ) & "," );
|
||
|
|
expected_value := expected( index );
|
||
|
|
assert_element_near( real_value, expected_value, abs_err, index );
|
||
|
|
index := index + 1;
|
||
|
|
end loop;
|
||
|
|
|
||
|
|
std.textio.write( data_file, "]" & LF );
|
||
|
|
file_close( data_file );
|
||
|
|
|
||
|
|
std.textio.write( std.textio.OUTPUT, TEST_OK );
|
||
|
|
end procedure check_and_write_content;
|
||
|
|
end package body test_data_channel_pkg;
|