143 lines
4.2 KiB
VHDL
143 lines
4.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.float_pkg.all;
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library work;
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use work.reg32.all;
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use work.avalon_slave.all;
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use work.test_utility.all;
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use work.test_avalon_slave.all;
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use work.task.all;
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use work.cosine_data.all;
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use work.test_hardware_task.all;
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use work.test_data_channel_pkg.all;
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library std;
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use std.env.all;
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use std.textio.all;
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entity test_task_cosine is
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generic( CHECK_RESULTS : boolean; GUI_MODE : boolean := false );
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end entity test_task_cosine;
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architecture test of test_task_cosine is
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procedure test_configure( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response ) is
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variable index : integer := 0;
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variable writedata : std_logic_vector( 31 downto 0 );
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begin
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std.textio.write( std.textio.OUTPUT, " test_configure ... " );
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index := 0;
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writedata := x"0147ae14"; -- 2^32 / 32
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write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
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index => index, config => writedata );
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index := 1;
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writedata := x"40000000";
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write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
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index => index, config => writedata );
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index := 2;
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writedata := x"40000000"; -- 2 ** 2 = 4 float
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write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
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index => index, config => writedata );
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std.textio.write( std.textio.OUTPUT, TEST_OK );
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end procedure test_configure;
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signal clk : std_logic := '0';
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signal reset : std_logic := '1';
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signal req : work.avalon_slave.Request;
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signal rsp : work.avalon_slave.Response;
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signal data_channel_req : work.avalon_slave.Request;
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signal data_channel_rsp : work.avalon_slave.Response;
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signal signal_write : std_logic;
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signal signal_writedata : std_logic_vector( 31 downto 0 );
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signal data_channel_read : std_logic;
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signal data_channel_readdata : std_logic_vector( 31 downto 0 );
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begin
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dut : entity work.task_sine
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port map (
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clk => clk,
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reset => reset,
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address => req.address,
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read => req.read,
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readdata => rsp.readdata,
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write => req.write,
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writedata => req.writedata,
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signal_write => signal_write,
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signal_writedata => signal_writedata
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);
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u_data_channel : entity work.data_channel
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port map (
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clk => clk,
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reset => reset,
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ctrl_address => data_channel_req.address,
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ctrl_read => data_channel_req.read,
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ctrl_readdata => data_channel_rsp.readdata,
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ctrl_write => data_channel_req.write,
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ctrl_writedata => data_channel_req.writedata,
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hw_sink_write => signal_write,
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hw_sink_writedata => signal_writedata,
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hw_source_read => data_channel_read,
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hw_source_readdata => data_channel_readdata
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);
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clk <= not clk after 10 ns;
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reset_release : process is
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begin
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wait for 35 ns;
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reset <= '0';
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wait;
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end process reset_release;
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stimulus: process is
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variable data_channel_config : std_logic_vector( 31 downto 0 ) := x"00000001";
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begin
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wait until falling_edge( reset );
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work.test_data_channel_pkg.write_and_assert_config( clk => clk,
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req => data_channel_req,
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rsp => data_channel_rsp,
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config => data_channel_config );
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test_configure( clk => clk, req => req, rsp => rsp );
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test_execute( clk => clk, req => req, rsp => rsp,
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write => signal_write, writedata => signal_writedata );
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if ( CHECK_RESULTS ) then
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check_and_write_content( clk => clk,
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req => data_channel_req, rsp => data_channel_rsp,
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expected => work.cosine_data.expected );
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else
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write_content( clk => clk,
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req => data_channel_req, rsp => data_channel_rsp );
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end if;
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if ( GUI_MODE ) then
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std.env.stop;
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else
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std.env.finish;
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end if;
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end process stimulus;
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end architecture test;
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