Studentenversion des ESY6/A Praktikums "signal_processing".
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vhdl.mk 482B

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  1. ghdl_version = $(shell ghdl --version 2> /dev/null)
  2. vsim_version = $(shell vsim -version 2> /dev/null)
  3. # in case verilog is part of the build a verilog capable simulator is required
  4. ifdef verilog_srcs
  5. ifneq (${vsim_version},)
  6. include ../questa-sim.mk
  7. else
  8. $(error No HDL simulation tool found for verilog!)
  9. endif
  10. else
  11. ifneq (${vsim_version},)
  12. include ../questa-sim.mk
  13. else
  14. ifneq (${ghdl_version},)
  15. include ../ghdl.mk
  16. else
  17. $(error No HDL simulation tool found!)
  18. endif
  19. endif
  20. endif