Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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counter_4bit.v 655B

3 years ago
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  1. // File: counter_4bit.v
  2. // Generated by MyHDL 0.11
  3. // Date: Mon Jun 7 19:39:23 2021
  4. `timescale 1ns/10ps
  5. module counter_4bit (
  6. clk,
  7. rst,
  8. data,
  9. updown,
  10. load,
  11. data_out
  12. );
  13. input clk;
  14. input rst;
  15. input [3:0] data;
  16. input updown;
  17. input load;
  18. output [3:0] data_out;
  19. reg [3:0] data_out;
  20. always @(posedge clk) begin: COUNTER_4BIT_CYCLE
  21. if (rst) begin
  22. data_out <= 0;
  23. end
  24. else if (load) begin
  25. data_out <= data;
  26. end
  27. else begin
  28. if (updown) begin
  29. data_out <= (data_out + 1);
  30. end
  31. else begin
  32. data_out <= (data_out - 1);
  33. end
  34. end
  35. end
  36. endmodule